Sudeep Mohanty
2ed15d8b1e
ulp: Added ULP RISC-V support for esp32s3
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This commit adds support for ULP RISC-V for esp32s3.
Signed-off-by: Sudeep Mohanty <sudeep.mohanty@espressif.com>
2022-01-18 10:58:00 +05:30
Jakob Hasse
81e9266204
[examples]: removed hyphens
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Replaced hyphens with underscores in examples
project definition for all examples which had
hyphens in their project name. dpp-enrollee is
an exceptions because the name matches the
project directory name while the project
directory also contains hyphens.
2021-10-09 13:58:24 +08:00
Marius Vikhammer
386739595f
RISCV-ULP: Add DS18B20 1wire RISCV-ULP example
2021-06-25 11:26:39 +08:00
Renz Bagaporo
754c8fcaa5
ci: modify ulp_riscv example to detect unintended wake
2021-03-31 17:15:55 +08:00
Renz Bagaporo
e5b3824f61
ci: add example test for ulp_riscv example
2021-02-26 13:34:09 +08:00
Angus Gratton
66d2c9196f
example ulp_riscv: Set IDF_TARGET to esp32s2
2020-12-24 14:18:02 +11:00
Angus Gratton
66fb5a29bb
Whitespace: Automated whitespace fixes (large commit)
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Apply the pre-commit hook whitespace fixes to all files in the repo.
(Line endings, blank lines at end of file, trailing whitespace)
2020-11-11 07:36:35 +00:00
Felipe Neves
b6dba84323
ulp: added support to building code for riscv ULP coprocessor
2020-07-15 15:28:49 -03:00
