8 Commits

Author	SHA1	Message	Date
Shubham Patil	8ad9daea7d	espcoredump: Parse bt for instruction fetch prohibited cause	2021-09-29 23:08:54 +05:30
dmitry	5d859f1404	Add Esp32s3 to the coredump component. ... Add changed expected_output for esp32, esp32s2 and esp32c3. coredump tag update.	2021-09-13 05:20:34 -04:00
Omar Chebib	83c9e1b223	freertos: take tasks snapshot out of tasks.c source code	2021-08-16 10:29:36 +08:00
Sachin Parekh	46dc36233a	coredump: Parse backtrace info for RISCV ... For RISCV, backtrace generation on device is not possible without including and parsing DWARF sections. We extract the crash task stack and let the host generate the backtrace	2021-05-17 11:43:25 +05:30
Fu Hanxi	d94423c1cf	fix(coredump): pr_status pid padding should be uint16	2021-04-26 20:44:23 +08:00
Shubham Patil	356e2bbe6d	espcoredump: On device core dump parsing to generate summary	2021-04-09 09:43:40 +05:30
Omar Chebib	e533431095	espcoredump: Fix bugs related to (fake) stacks ... Add support to tasks stacks in RTC DRAM. Before this fix, any stack in RTC DRAM would have been considered as corrupted, whichi is not the case. Fix a bug related to wrong parameters passed to esp_core_dump_get_stack. Fix a bug reading fake stack memory, triggering a memory violation. * Closes https://github.com/espressif/esp-idf/issues/6751 * Merges https://github.com/espressif/esp-idf/pull/6750	2021-03-22 11:38:21 +08:00
Omar Chebib	e9996ebd4b	espcoredump: code refactoring and add support for RISC-V implemetation ... This commit includes the refactoring of the core dump feature. Thanks to this refactoring, it is easier to integrate the support of RISC-V architecture for this feature. Fixes ESP-1758	2021-02-07 19:04:19 +08:00