Commit Graph

21 Commits

Author SHA1 Message Date
Marius Vikhammer
8ac74082f1 soc: add dummy bytes to ensure instr prefetch always valid
The CPU might prefetch instructions, which means it in some cases
will try to fetch instruction located after the last instruction in
flash.text.

Add dummy bytes to ensure fetching these wont result in an error,
 e.g. MMU exceptions
2021-03-29 13:50:03 +08:00
Renz Bagaporo
115b6ac0ac esp32: transfer coredump linker script blocks to ldgen 2021-03-01 14:19:34 +08:00
Angus Gratton
55155c3f82 esp_system: Rename _init_start symbol to _vector_table 2020-12-24 13:40:01 +11:00
Angus Gratton
66fb5a29bb Whitespace: Automated whitespace fixes (large commit)
Apply the pre-commit hook whitespace fixes to all files in the repo.

(Line endings, blank lines at end of file, trailing whitespace)
2020-11-11 07:36:35 +00:00
Martin Vychodil
497b730e8f * memprot support for RTC_SLOW
* API upgrade
JIRA IDF-1636
2020-10-08 11:19:23 +08:00
Angus Gratton
4a0a331122 Merge branch 'bugfix/esp32s2_return_use_fixed_static_ram_size_option' into 'master'
esp32s2: Add USE_FIXED_STATIC_RAM_SIZE feature

Closes IDF-1800

See merge request espressif/esp-idf!9033
2020-07-14 13:14:07 +08:00
Mahavir Jain
e62cb2be68 esp32s2: remove bt references from esp32s2 ld script 2020-07-02 03:45:05 +00:00
Renz Christian Bagaporo
0f43a2620d esp_system: component init functions macro
Allows components to declare initialization function, such that the
startup code does not have direct dependency on the component.
2020-06-19 18:40:09 +10:00
KonstantinKondrashov
96b3ab708a esp32s2: Add USE_FIXED_STATIC_RAM_SIZE feature
This feature exists on ESP32 and missed for ESP32S2. This commit adds it for esp32s2 as well.

Closes: IDF-1800
2020-06-17 22:24:51 +08:00
Alexey Gerenkov
1deeadf4c5 Added coredump user defined variable into coredump 2020-06-15 02:35:38 +08:00
Angus Gratton
59f29cbca8 Merge branch 'feature/allow_rtc_memory_for_task_stacks' into 'master'
Add RTC Fast Memory to Dynamic Memory Pool

See merge request espressif/esp-idf!8390
2020-05-29 14:07:01 +08:00
jiangguangming
b25ccde45f flash mmap: fix bug for cache2phys and phys2cache on esp32s2 2020-05-26 15:14:23 +08:00
Mahavir Jain
18c1838587 esp32s2: add config option to place RTC data in fast RAM 2020-05-14 13:12:26 +00:00
Sachin Parekh
46d914ff45 gdb: Modify PC in case of invalid PC
Signed-off-by: Sachin Parekh <sachin.parekh@espressif.com>
2020-05-08 18:34:52 +05:30
Ivan Grokhotkov
275ed32a11 Merge branch 'feature/esp32s2_iram_dram_protection' into 'master'
esp32s2: IRAM/DRAM memory protection

See merge request espressif/esp-idf!8156
2020-04-23 21:52:54 +08:00
Martin Vychodil
7491ea677a esp32s2: IRAM/DRAM memory protection
* new mem_prot API
* mem_prot on & locked by default (see Kconfig)
* feature activated in start_cpu0_default()

JIRA IDF-1355
2020-04-21 15:10:58 +02:00
Jakob Hasse
4943b1cbf0 CXX: make __attribute__((init_priority(n))) work
* Added corresponding test case
* Moved all C++ init tests to separate file

Closes https://github.com/espressif/esp-idf/issues/5038
2020-04-08 09:11:54 +08:00
Ivan Grokhotkov
110f3c9ff5 esp32s2: put static .data and .bss directly after .iram.text
This results in a single large heap section instead of two smaller
ones.

Closes IDF-1354
2020-01-24 10:48:38 +01:00
Ivan Grokhotkov
27bff3517f esp32s2: fix "loadable ELF" build
Closes IDF-1346
2020-01-24 10:48:20 +01:00
Ivan Grokhotkov
cbb84e8f5e esp32s2: fix THREADPTR calculation, re-enable FreeRTOS TLS tests
1. Clarify THREADPTR calculation in FreeRTOS code, explaining where
the constant 0x10 offset comes from.

2. On the ESP32-S2, .flash.rodata section had different default
alignment (8 bytes instead of 16), which resulted in different offset
of the TLS sections. Unfortunately I haven’t found a way to query
section alignment from C code, or to use a constant value to define
section alignment in the linker script. The linker scripts are
modified to force a fixed 16 byte alignment for .flash.rodata on the
ESP32 and ESP32-S2beta. Note that the base address of .flash.rodata
was already 16 byte aligned, so this has not changed the actual
memory layout of the application.

Full explanation of the calculation below.

Assume we have the TLS template section base address
(tls_section_vma), the address of a TLS variable in the template
(address), and the final relocation value (offset). The linker
calculates:
offset = address - tls_section_vma + align_up(TCB_SIZE, alignment).

At run time, the TLS section gets copied from _thread_local_start
(in .rodata) to task_thread_local_start. Let’s assume that an address
of a variable in the runtime TLS section is runtime_address.
Access to this address will happen by calculating THREADPTR + offset.
So, by a series of substitutions:

THREADPTR + offset = runtime_address THREADPTR = runtime_address - offset
THREADPTR = runtime_address - (address - tls_section_vma + align_up(TCB_SIZE, alignment)) THREADPTR = (runtime_address - address) + tls_section_vma - align_up(TCB_SIZE, alignment)

The difference between runtime_address and address is same as the
difference between task_thread_local_start and _thread_local_start.
And tls_section_vma is the address of .rodata section, i.e.
_rodata_start. So we arrive to

THREADPTR = task_thread_local_start - _thread_local_start + _rodata_start - align_up(TCB_SIZE, alignment).

The idea with TCB_SIZE being added to the THREADPTR when computing
the relocation was to let the OS save TCB pointer in the TREADPTR
register. The location of the run-time TLS section was assumed to be
immediately after the TCB, aligned to whatever the section alignment
was. However in our case the problem is that the run-time TLS section
is stored not next to the TCB, but at the top of the stack. Plus,
even if it was stored next to the TCB, the size of a FreeRTOS TCB is
not equal to 8 bytes (TCB_SIZE hardcoded in the linker). So we have
to calculate THREADPTR in a slightly obscure way, to compensate for
these differences.

Closes IDF-1239
2020-01-23 11:29:22 +01:00
morris
e30cd361a8 global: rename esp32s2beta to esp32s2 2020-01-22 12:14:38 +08:00