Commit Graph

211 Commits

Author SHA1 Message Date
Renz Bagaporo
ae15c81dbe esp_common: move to esp_hw_support 2021-02-24 12:16:37 +08:00
Mahavir Jain
880a63b2e9 esp_system: make rtc fast memory to heap configuration unified across chips
Closes IDF-2503
2020-12-24 09:46:35 +05:30
chaijie
a48b5246cc ESP32: Fix xtal 32k not oscillate or oscillate too slowly issue
ESP32 in revision0 and revision1 uses touchpad to provide
current to oscillate xtal 32k. But revision2 and revision3
do not need to do that.
Note: touchpad can not work and toupad/ULP wakeup sources
are not available when toupad provides current to xtal 32k
2020-11-23 19:38:11 +08:00
Angus Gratton
66fb5a29bb Whitespace: Automated whitespace fixes (large commit)
Apply the pre-commit hook whitespace fixes to all files in the repo.

(Line endings, blank lines at end of file, trailing whitespace)
2020-11-11 07:36:35 +00:00
KonstantinKondrashov
e9978f7623 esp32xx: Fix default values for all RTC sources in RTC_CLK_CAL_CYCLES option
Closes: https://github.com/espressif/esp-idf/issues/6037
2020-10-28 16:25:07 +08:00
Konstantin Kondrashov
9386cafbc3 time: Fix gettimeofday for ESP32-S3 2020-10-20 14:09:32 +08:00
Renz Bagaporo
f33f49331f ci: update configs to include/exclude esp_pm in unit test 2020-09-25 05:24:10 +00:00
Renz Bagaporo
6462f9bfe1 esp32, esp32s2: create esp_pm component 2020-09-25 05:24:10 +00:00
Wang Fang
a50966cf7a docs: update the description for RTC Clock Sources for esp32 and esp32s2 2020-09-23 17:13:19 +08:00
Angus Gratton
3755fb6597 Merge branch 'feature/add_esp32s3_bootloader_ld_file' into 'master'
move part of esp32-s3 codes to master (bootloader linker, esp32s3 empty componnet)

See merge request espressif/esp-idf!9608
2020-07-21 14:51:04 +08:00
Angus Gratton
c09fdc0b09 esp32: Use package identifier to look up SPI flash/PSRAM WP Pin, unless overridden
Allows booting in QIO/QOUT mode or with PSRAM on ESP32-PICO-V3 and
ESP32-PICO-V3-O2 without any config changes.

Custom WP pins (needed for fully custom circuit boards) should still be compatible.
2020-07-20 14:08:49 +08:00
chenjianqiang
9de04b9f5f feat(psram): support 16Mbit PSRAM for esp32 2020-07-20 12:21:32 +08:00
morris
6316e6eba2 esp_system: add CONFIG_ESP_SYSTEM_RTC_EXT_CRYS 2020-07-20 11:15:24 +08:00
Li Shuai
72f583dfa7 add soft solution for esp32 eco3 live lock issue 2020-06-05 06:04:18 +00:00
Mahavir Jain
1aac284dda heap: add rtc fast memory region to dynamic pool
- for ESP32 only enabled in case of unicore config
- capability wise this region (8K) is same as DRAM, except non-DMA capable
- also fixed small issue in reserved memory region processing when (start == end)
2020-05-14 13:12:26 +00:00
Jiang Jiang Jian
3feffdfe03 Merge branch 'bugfix/psram_single_bit_error' into 'master'
bugfix(psram): support psram 2T mode to fix single bit error

See merge request espressif/esp-idf!6936
2020-04-10 15:04:15 +08:00
Ivan Grokhotkov
168660aebf Merge branch 'feature/toolchain_2020r1-RC1' into 'master'
Toolchain 2020r1 support bringing (esp32, esp32s2)

See merge request espressif/esp-idf!7509
2020-04-01 18:17:28 +08:00
Jeroen Domburg
419848549e Add fixes for gcc8 psram fix improvement 2020-03-27 20:04:47 +07:00
KonstantinKondrashov
a259746016 esp32: Add a Kconfig option- Number of attempts to repeat 32k XTAL calibration
Closes: IDF-1479
2020-03-27 04:56:44 +00:00
chenjianqiang
04781fb009 psram: improve 2T mode enable
1. recover psram bankswitch config
2. set 2T mode enable default config as n
3. remove PSRAM ID check
2020-03-25 18:39:50 +08:00
chenjianqiang
55a20033e7 bugfix(psram): support psram 2T mode to fix single bit error
1. add enable PSRAM 2T mode function
2. enable PSRAM 2T mode base on PSRAM ID
3. abort when himem and 2T mode are enabled meanwhile
4. set SPIRAM_2T_MODE as "y" by default and modify SPIRAM_BANKSWITCH_ENABLE as "n" by default
2020-03-25 18:29:32 +08:00
Renz Christian Bagaporo
2b100789b7 esp32, esp32s2: move panic handling code to new component 2020-03-10 19:56:24 +08:00
Sachin Parekh
301dacfb33 Exception handlers for LoadStoreError and LoadStoreAlignmentError
Configurable option to use IRAM as byte accessible memory (in single core mode) using
load-store (non-word aligned and non-word size IRAM access specific) exception handlers.
This allows to use IRAM for use-cases where certain performance penalty
(upto 170 cpu cycles per load or store operation) is acceptable. Additional configuration
option has been provided to redirect mbedTLS specific in-out content length buffers to
IRAM (in single core mode), allows to save 20KB per TLS connection.
2020-02-26 20:21:59 +08:00
Konstantin Kondrashov
739eb05bb9 esp32: add implementation of esp_timer based on TG0 LAC timer
Closes: IDF-979
2020-02-06 14:00:18 +08:00
morris
e1f9b283bc esp32s2: mac addr allocation 2020-01-14 15:19:38 +08:00
Alexey Gerenkov
30ff7198b8 apptrace: Renames Kconfig options 2019-11-13 15:24:01 +03:00
Michael (XIAO Xufeng)
748b79e94a ci: fix one ut issue when using Wrover-B module with newer ver of PSRAM
The workaround for PSRAM that will occupy an SPI bus is enabled only when:

1. used on 32MBit ver 0 PSRAM.
2. work at 80MHz.

The test used to only check 32MBit by the config option, but for PSRAM
on Wrover-B module seems to use a newer version of 32MBit PSRAM.  So it
expects the workaround to be enabled, but actually not.

This commit split the unit test into two parts:

1. check all SPI buses are available, for all configs except psram_hspi
and psram_vspi, run on regular runners (including Wrover and Wrover-B).
a hidden option is enabled so that the compiler knows it's not building
psram_hspi or psram_vspi.

2. check the specified bus are acquired, for config psram_hspi and
psram_vspi. This only run on special runner (legacy Wrover module).
2019-11-03 03:07:37 +00:00
Ivan Grokhotkov
faa219acdb freertos: fix defining uxTopUsedPriority for esp32s2beta 2019-10-29 16:38:48 +01:00
Angus Gratton
496ede9bcd Merge branch 'master' into feature/esp32s2beta_merge 2019-10-15 14:59:27 +11:00
Ivan Grokhotkov
751b60b171 Merge branch 'feature/add_psram_workaround_option' into 'master'
make psram workaround depend on chip revison

Closes IDF-1004

See merge request espressif/esp-idf!6113
2019-10-09 23:41:09 +08:00
Ivan Grokhotkov
5830f529d8 Merge branch 'master' into feature/esp32s2beta_merge 2019-10-02 19:01:39 +02:00
Ivan Grokhotkov
c496268b10 Merge branch 'feature/load_elf' into 'master'
Support ELF files loadable with gdb

Closes IDF-335

See merge request espressif/esp-idf!5779
2019-09-27 19:36:25 +08:00
Roland Dobai
5a916ce126 Support ELF files loadable with gdb 2019-09-24 07:19:50 +00:00
Roland Dobai
833822c10b Fix Kconfig issues discovered by upstream Kconfiglib 2019-09-23 16:10:57 +02:00
Angus Gratton
adfc06a530 Merge branch 'master' into feature/esp32s2beta_merge 2019-09-20 10:28:37 +10:00
suda-morris
77eb32b710 make psram workaround depend on chip revison
Since ESP32 revision 3, the PSRAM workaround is not needed.
2019-09-19 13:20:34 +08:00
Ivan Grokhotkov
bf68285689 Merge branch 'feature/compile_option_O0' into 'master'
build_system: add new compiler optimization levels

See merge request espressif/esp-idf!5686
2019-09-17 16:54:55 +08:00
Andrew
4fdaeb6b6e cmake: Add new compiler optimization levels definitions
Rename and add multiple kconfig compiler options. New compiler options
COMPILER_OPTIMIZATION_PERF and COMPILER_OPTIMIZATION_NONE have been added.
Optimize "Debug" and "Release" options to "Default" and "Size" respectively.
This commit also does the following:

- The COMPILER_OPTIMIZATION_PERF option introduced multiple bug.
This commit fixes those bugs.
- build.yml also updated to test for the new optimization options.
2019-09-06 17:37:19 +08:00
Alex Lisitsyn
7ff9538c48 espcoredump: fix issue with spi_flash access
spi_flash has been updated and its functions work from flash by default instead of IRAM that cause issue
add Kconfig value into espcoredump to enable spi_flash legacy mode (CONFIG_SPI_FLASH_USE_LEGACY_IMPL) when core dump is selected
fix spi_flash issues to work correctly with legacy mode when CONFIG_SPI_FLASH_USE_LEGACY_IMPL is used
2019-09-06 15:37:55 +08:00
Angus Gratton
6990a7cd54 Merge branch 'master' into feature/esp32s2beta_update 2019-08-19 15:03:43 +10:00
suda-morris
f86e82cb63 efuse: update the scheme of getting chip revision 2019-08-13 10:59:02 +08:00
Angus Gratton
24d26fccde Merge branch 'master' into feature/esp32s2beta_update 2019-08-08 13:44:24 +10:00
Ivan Grokhotkov
7d21ece78b gdbstub: move to a separate component, support multiple targets 2019-07-17 16:01:03 +02:00
Konstantin Kondrashov
632b016028 esp32: Dis interrupts up to 5 lvl for DPORT
Disable interrupts for both DPORT workarounds up to 5 lvl.

Closes: https://esp32.com/viewtopic.php?f=2&t=10981&sid=d125cec233070ed4d2c5410bf5d3d74a
Closes: IDF-728
2019-07-16 05:54:45 +00:00
Ivan Grokhotkov
66e0b2f9df gdbstub: move to a separate component, support multiple targets 2019-07-02 11:06:25 +02:00
Xia Xiaotian
99ef587a05 run WiFi on ESP32SBETA 2019-06-28 11:34:49 +08:00
suda-morris
3f7a571c90 fix errors when ci testing for esp32 2019-06-19 15:31:47 +08:00
Angus Gratton
ddbd09eb15 esp32/esp32s2beta: Extract common SPIRAM options into esp_commmon component 2019-06-11 13:07:37 +08:00
Angus Gratton
8d949c3c9d esp32s2beta: Apply new Kconfig names to esp32s2beta
Still using ESP32_xxx prefix on all chips: CORE_DUMP, APP_TRACE

Still using the same config prefix and duplicate names in esp32 & esp32s2beta: SPIRAM, PM
2019-06-11 13:07:37 +08:00
Gautier Seidel
542e544faa esp32: Allow fixed static RAM size and DRAM heap size
Merges https://github.com/espressif/esp-idf/pull/3222
2019-06-06 18:23:04 +10:00