6 Commits

Author	SHA1	Message	Date
Shubham Patil	aa89d67923	espcoredump: Parse bt for instruction fetch prohibited cause	2022-02-01 18:28:30 +05:30
Sachin Parekh	e0fc13b23d	coredump: Parse backtrace info for RISCV ... For RISCV, backtrace generation on device is not possible without including and parsing DWARF sections. We extract the crash task stack and let the host generate the backtrace	2022-02-01 17:52:13 +05:30
Shubham Patil	9928f44894	espcoredump: On device core dump parsing to generate summary	2022-02-01 15:24:16 +05:30
Fu Hanxi	f9cf648afd	fix(coredump): pr_status pid padding should be uint16	2022-01-18 13:50:10 +08:00
Omar Chebib	a573cfe58a	espcoredump: Fix bugs related to (fake) stacks ... Add support to tasks stacks in RTC DRAM. Before this fix, any stack in RTC DRAM would have been considered as corrupted, whichi is not the case. Fix a bug related to wrong parameters passed to esp_core_dump_get_stack. Fix a bug reading fake stack memory, triggering a memory violation. * Closes https://github.com/espressif/esp-idf/issues/6751 * Merges https://github.com/espressif/esp-idf/pull/6750	2021-05-28 01:58:09 +00:00
Omar Chebib	113bf479a4	espcoredump: code refactoring and add support for RISC-V implemetation ... This commit includes the refactoring of the core dump feature. Thanks to this refactoring, it is easier to integrate the support of RISC-V architecture for this feature. Fixes ESP-1758	2021-03-10 12:19:00 +08:00