Commit Graph

77 Commits

Author SHA1 Message Date
morris
f5b03c9ea3 misc adjustment of esp32 component 2019-04-03 19:57:46 +08:00
Ivan Grokhotkov
060cf9d6b4 Merge branch 'power_management/i2s+i2c' into 'master'
Power management/i2s+i2c

See merge request idf/esp-idf!4338
2019-03-19 17:27:59 +08:00
Ivan Grokhotkov
f0a82d7185 driver/i2c: write i2c command structure to hardware in one operation
GCC compiler can generate 8-bit stores when modifying bitfields of
volatile structs (https://github.com/espressif/esp-idf/issues/597).
In the specific case of I2C driver, this resulted in byte_num field
to be written using s8i. However the peripheral requires 32-bit
writes, and ignores 8-bit writes. This change modifies the code to
compose the 32-bit command register value first, and then write the
complete value to the hardware.
2019-03-18 18:23:50 +08:00
Sachin Parekh
d0234ad24a I2C: Enable Power Management locks
Acquires PM_APB_FREQ_MAX lock when carrying any transaction on I2C if
Power Management Framework is enabled.

Signed-off-by: Sachin Parekh <sachin.parekh@espressif.com>
2019-03-18 08:21:21 +00:00
Wangjialin
924daf7b84 bugfix(i2c): reduce speed of I2C master bus reset routine and release SDA
closes https://github.com/espressif/esp-idf/issues/2494
closes https://github.com/espressif/esp-idf/pull/2493
closes https://github.com/espressif/esp-idf/pull/2496

1. Change bus reset to handle interrupted READ sequences.
2. Slow down I2C to 100khz during reset
3. If a SLAVE device was in a read operation when the bus was interrupted, the SLAVE device is controlling SDA.The only bit during the 9 clock cycles of a byte READ the MASTER(ESP32) is guaranteed control over, is during the ACK bit period.
If the SLAVE is sending a stream of ZERO bytes, it will only release SDA during the ACK bit period. The master(ESP32) cannot generate a STOP unless SDA is HIGH. So, this reset code synchronizes the bit stream with, Either, the ACK bit, Or a 1 bit.
2018-11-30 10:08:28 +08:00
chuck todd
e55f9c1e98 1. Slow down I2C to 100khz During Reset
I am stealing this delay coding from @jeremyherbert #2493 pr.

2. Change Bus Reset to handle interrupted READ sequences.

The current code does not handle interrupted READ cycles.

 If a SLAVE device was in a read operation when the bus was interrupted, the SLAVE device is controlling SDA.

The only bit during the 9 clock cycles of a byte READ the MASTER(ESP32) is guaranteed control over, is during the ACK bit period.

If the SLAVE is sending a stream of ZERO bytes, it will only release SDA during the ACK bit period. The master(ESP32) cannot generate a STOP unless SDA is HIGH.

So, this reset code synchronizes the bit stream with, Either, the ACK bit, Or a 1 bit.

3. fix typo

correct `sda_id` to `sda_io` in `i2c_master_clear_bus()` @ryan-ma found it.  This typo was generated when I manually edited this patch on GitHub, I should have done a Copy/Paste operation!
2018-11-30 10:08:28 +08:00
jeremy
34c1d25c7f reduce speed of i2c master bus reset routine and release sda 2018-11-30 10:08:28 +08:00
morris
2b165f99c4 i2c_tool: add i2c_tool example test
1. add example test for i2c-tools
2. make command line arguments number configurable
2018-11-30 10:08:28 +08:00
kooho
33138a3dec driver(i2c): enable I2C master hardware filter by default. 2018-11-23 10:27:59 +08:00
Angus Gratton
a67d5d89e0 Replace all DOS line endings with Unix
Command run was:
git ls-tree -r HEAD --name-only | xargs dos2unix
2018-07-12 19:10:37 +08:00
kooho
f6f9f93a9d driver(i2c, rmt):Add intr_flag setting to ESP_INTR_FLAG_IRAM support when enable psram. 2018-05-21 09:37:56 +08:00
kooho
37db055cff driver(i2c): Fixed ack_err interrupt can't exit bug. 2018-03-26 16:31:17 +08:00
Per Malmberg
5fb16d9b2b Fix regression in i2c_master_read() which rejected all data lenths. 2017-12-28 14:54:15 +01:00
kooho
d78be97154 add NACK for the last byte to read 2017-12-26 21:50:18 +08:00
Angus Gratton
661d584ae7 Merge branch 'bugfix/i2c_fixes_pr1180' into 'master'
i2c: rx <-> tx typo's, NULLing free'd variable, consistent CRITICAL sects

See merge request !1551
2017-12-18 06:44:33 +08:00
Chuck Todd
d913fff6d7 i2c: rx <-> tx typo's, NULLing free'd variable, consistent CRITICAL sects
A couple of typos referencing tx_ring_buf when rx_ring_buf, slv_tx_mux
instead of slv_rx_mux.

Also, I2C_ENTER_CRITICAL()/I2C_EXIT_CRITICAL() usage was not consistent.
Only some of the _set_ functions had them.  Most of the _get_ function
had them?  It is my understanding that they should be wrapped around
writes, not reads? (I think we still need the lock for reading pairs of consistent values)

Also, the ticks_to_wait timeout handling in i2c_master_cmd_begin() would
not handle integer rollover correctly.

Merges https://github.com/espressif/esp-idf/pull/1180
2017-12-11 11:08:39 +08:00
Fabiano Kovalski
9075b507b5 driver(i2c): corrected timeout range for i2c_set_timeout.
Merges https://github.com/espressif/esp-idf/pull/1353
2017-12-08 14:26:35 +08:00
Wangjialin
bf3c41bb92 bugfix(i2c): use queue instead of event group for internal commands
Reported from github:
https://github.com/espressif/esp-idf/issues/1312
https://github.com/espressif/esp-idf/issues/1193

Issues:
1. We used to use event group in the driver, which would cause:
    a. longer operation time since the event group are based on FreeRTOS timer.
    b. Operation fails if the timer queue is not long enough.
2. There might be some issue with event group, we will still try to provide a small test code in other branch.

modification:
1. use queue instead of event-bit for internal commands
2. use queue overwrite for cmd_done event
2017-11-29 12:33:11 +08:00
Wangjialin
ed1e32f583 bugfix(i2c): add I2C hardware reset if the hw FSM get stuck
Reported from different sources from github or bbs:

https://github.com/espressif/esp-idf/issues/680

https://github.com/espressif/esp-idf/issues/922

We tested reading several sensor or other I2C slave devices, if the power and SDA/SCL wires are in proper condition, everything works find with reading the slave.
If we remove the power supply for the slave during I2C is reading, or directly connect SDA or SCL to ground, this would  cause the I2C FSM get stuck in wrong state, all we can do is the reset the I2C hardware in this case.
After this commit, no matter whether the power supply of I2C slave is removed or SDA / SCL are shorted to ground, the driver can recover from wrong state.

We are not sure whether this the save issue with the reported one yet, but to make the driver more robust.

Further information:

1. For I2C master mode, we have tested different situations, e.g., to short the SDA/SCL directly to GND/VCC, to short the SDA to SCL, to un-plug the slave device, to power off the slave device. Under all of those situations, this version of driver can recover and keep working.
2. Some slave device will die by accident and keep the SDA in low level, in this case, master should send several clock to make the slave release the bus.
3. Slave mode of ESP32 might also get in wrong state that held the SDA low, in this case, master device could send a stop signal to make esp32 slave release the bus.

Modifications:

1. Disable I2C_MASTER_TRAN_COMP interrupt to void extra interrupt.
2. Disable un-used timeout interrupt for slave.
3. Add bus reset if error detected for master mode.
4. Add bus clear if SDA level is low when error detected.
5. Modify the argument type of i2c_set_pin.
6. add API to set timeout value
7. add parameter check for timing APIs
2017-10-21 02:10:59 +08:00
Angus Gratton
a89e93fc3d i2c driver: When deleting, disable interrupts before freeing data structures
Fixes a potential race if I2C interrupt occurs while driver is being delted.
2017-06-08 15:57:31 +10:00
jack
fc130fba86 fix bug that files missing commit in MR 773 2017-05-31 19:37:39 +08:00
Michel Pollet
349a77cb55 components/driver: 'const' all config calls.
Some were, some weren't. They all could/should be.

Signed-off-by: Michel Pollet <buserror@gmail.com>
2017-04-13 18:33:33 +01:00
Ivan Grokhotkov
91d35f01f2 Merge branch 'bugfix/i2c_spikes_on_master_init_#393_from_github' into 'master'
bugfix: I2C spikes on master init

Fix I2C spikes on master init.
Before I2C io init, set high level on SDA/SCK IOs.

Fixes https://github.com/espressif/esp-idf/issues/393

See merge request !593
2017-03-21 15:09:16 +08:00
Wangjialin
1ad68de8b8 bugfix: I2C spikes on master init #393 from github
Fix I2C spikes on master init.
This issue is reported from https://github.com/espressif/esp-idf/issues/393
Before I2C io init, set high level on SDA/SCK IOs.
2017-03-19 17:05:07 +08:00
Wangjialin
94b91ee4af bugfix: i2c driver not working in 'RELEASE' configuration
This issue is reported from https://github.com/espressif/esp-idf/issues/304.
We found that when we operate the hw command registers in I2C struct, sometimes the behaviour would be different in DEBUG/RELEASE optimisation level:

The code looks like this:
I2C[i2c_num]->command[p_i2c->cmd_idx].byte_num -= 0;

In DEBUG configuration:
I2C[i2c_num]->command[p_i2c->cmd_idx].byte_num -= 0;
400f3ab0:    3388          l32i.n    a8, a3, 12
400f3ab2:    14c882            addi    a8, a8, 20
400f3ab5:    a08840            addx4    a8, a8, a4
400f3ab8:    0020c0            memw
400f3abb:    2898          l32i.n    a9, a8, 8
400f3abd:    0020c0            memw
400f3ac0:    28b8          l32i.n    a11, a8, 8
400f3ac2:    74a090            extui    a10, a9, 0, 8
400f3ac5:    00af92            movi    a9, 0xffffff00
400f3ac8:    109b90            and    a9, a11, a9
400f3acb:    2099a0            or    a9, a9, a10
400f3ace:    0020c0            memw
400f3ad1:    2899          s32i.n    a9, a8, 8

In RELEASE configuration:
I2C[i2c_num]->command[p_i2c->cmd_idx].byte_num -= 0;
400f2ba2:    580572            l8ui    a7, a5, 88
400f2ba5:    747070            extui    a7, a7, 0, 8
400f2ba8:    0020c0            memw
400f2bab:    584572            s8i    a7, a5, 88

Looks like the compiler will make it a 8bit operation after optimisation.
But the register value changes from 0x901 to 0x101.
After this 8-bit optimisation, the 11th bit changed from 1 to zero, which caused this error.

We are still trying to find out why that happens, because there might be some risk when operating the register struct.
This is a workaround to avoid "-=" operation on I2C register struct fields.
2017-03-19 16:09:44 +08:00
devsaurus
d8fb30c930 i2c: fix i2c_get_period name
rename i2s_get_period to i2c_get_period
2017-01-16 02:37:10 +08:00
Wangjialin
9c7cc86793 1. modify i2c_set_pin function
2. update example comments and other minor changes
3. rename API:  i2c_cmd_link_create/i2c_cmd_link_delete (+4 squashed commits)

Squashed commits:
[2e0ac3e] 1. coding style: add one space after condition key words.
2. modify i2c.h, use gpio_num_t instead of int, improve comments of return values
3. add i2c index in index.rst
4. add readme for i2c example
[4991d92] update i2c.doc
[88b672e] driver: i2c

1. add mux and spin lock to run in a thread-safe way.
2. modify example code
[4eb15fe] driver: i2c code

1. add i2c master code
2. add i2c slave code
3. add i2c example code
4. add DRAM_ATTR for I2C array
2017-01-03 00:57:19 +08:00