Commit Graph

12 Commits

Author SHA1 Message Date
Marius Vikhammer
eec2419390 system: enable shared stack watchpoint
Enable shared stack watchpoint for overflow detection

Enable unit tests:
 * "test printf using shared buffer stack" for C3
 * "Test vTaskDelayUntil" for S2
 * "UART can do poll()" for C3
2021-02-18 15:38:30 +08:00
Ivan Grokhotkov
bb1f75179b Merge branch 'bugfix/freertos_systimer_stall_when_cpu_halted' into 'master'
freertos: stall systimer while CPU is in debug mode

See merge request espressif/esp-idf!12063
2021-01-29 07:02:30 +08:00
Ivan Grokhotkov
b2aaebaf85 freertos: add thread local storage support in RISC-V port 2021-01-24 12:38:15 +00:00
Ivan Grokhotkov
d7bac619ec freertos: stall systimer while CPU is in debug mode 2021-01-24 11:32:17 +00:00
Li Shuai
63c4e5481f fix no RTOS SysTick interrupt for a period of time after the OS Scheduler is started 2021-01-19 14:51:22 +08:00
Li Shuai
355dd10257 light sleep: dfs support for esp32c3 2021-01-19 14:50:58 +08:00
Jakob Hasse
b51889dccb system: stack watchpoint support on C3
Closes IDF-2307
2021-01-14 17:46:44 +08:00
morris
9e7d2c0065 esp32c3: format and clean up interrupt and os port code 2021-01-05 15:39:46 +08:00
Felipe Neves
f4781d3b1d freertos: riscv port now uses interrupt allocator and crosscore interrupt 2021-01-05 15:39:46 +08:00
Felipe Neves
810be86f21 freertos/riscv: move freertos aware interrupt code from vectors to the freertos riscv port.
The riscv vectors.S in riscv component contains the trap vector, which is responsible to
defer interrupts and examine if a task context switch is needed, this change cleans up
this code by hiding all freertos details behind on two functions rtos_it_enter/exit and
their implementations are placed in freertos riscv port files.
2021-01-05 15:39:46 +08:00
Angus Gratton
5228d9f9ce esp32c3: Apply one-liner/small changes for ESP32-C3 2020-12-01 10:58:50 +11:00
Angus Gratton
87e13baaf1 freertos: Add RISC-V port
Changes come from internal branch commit a6723fc
2020-11-13 07:49:11 +11:00