Commit Graph

125 Commits

Author SHA1 Message Date
ChenJianxing
0a8ba88145 esp_wifi: optimization wifi rate
1.support disable 11b rate
2.support config espnow rate
3.fix sta negotiate phymode issue
4.update ftm rate
2021-02-25 10:21:46 +00:00
dongyou
059ffa6daf change rom function for esp32c3 to fix eb lldesc size issue 2021-02-24 17:45:07 +08:00
morris
bf2480f62d efuse: can disable boot ROM log from Kconfig 2021-02-22 20:56:43 +08:00
morris
0f5d1c1c46 rtc: supported disable rom log temporarily 2021-02-22 20:56:43 +08:00
Angus Gratton
49c442b12f Merge branch 'feature/efuse_update_description' into 'master'
efuse: Updates description of uart_print_control efuse

Closes IDF-2705

See merge request espressif/esp-idf!12236
2021-02-09 11:02:26 +08:00
Xia Xiaotian
b71481093a esp_wifi: fix some Wi-Fi scan and coexist bugs
1. Fix the bug that Wi-Fi performance is impacted by BLE starting scan for a while in some scenarios on ESP32-C3.

2. Fix the bug that Wi-Fi performance is impacted when Bluetooth change state for a while in some scenarios on ESP32-C3.

3. Fix the bug that BLE performance is impacted by Wi-Fi scan on ESP32-C3.

4. Fix the bug that Wi-Fi scan fails when BLE is scanning on ESP32-C3.

5. Fix Wi-Fi ACK and CTS rate when low rate is disabled on ESP32-C3.
2021-02-08 21:20:09 +08:00
KonstantinKondrashov
43ebb8ea61 efuse: Updates description of uart_print_control efuse 2021-02-08 18:02:55 +08:00
Jiang Jiang Jian
d1cc9e98b7 Merge branch 'bugfix/fix_wifi_connect_fail' into 'master'
WiFi: fix the bug that wifi connect fail for ESP32C3

See merge request espressif/esp-idf!12308
2021-02-06 02:35:43 +08:00
Jack
2859c7ebd1 fix the bug that wifi connect fail 2021-02-06 00:12:37 +08:00
Cao Sen Miao
c1b41ece32 flash_encryption: Quick fixed the issue that block when flash_encryption_write, Related https://github.com/espressif/esp-idf/issues/6322, Related https://github.com/espressif/esp-idf/issues/6254 2021-02-05 20:10:42 +08:00
Jiang Jiang Jian
28faf93c51 Merge branch 'feature/esp32c3_power_down' into 'master'
esp32c3 : power down MAC and BB only if both Wi-Fi and BT power down

Closes FC3-99

See merge request espressif/esp-idf!12076
2021-01-28 23:27:19 +08:00
baohongde
eef66789d4 Mac BB power down in light sleep
components/bt: Do not use feature: timer support isr dispatch method

disable controller after wake up finished.

protect critical section of power down

choose clk in sleep

components/coex: mac bb power down in light sleep

components/coex: Macro changed

components/os: protect reserved interrupt number

update phy to phy_version 300,6e46ba7,Jan 25 2021

some bugfix
2021-01-28 22:28:04 +08:00
Ivan Grokhotkov
9a20283485 Merge branch 'bugfix/scan_test_missing_build_apps_without_tests' into 'master'
ci: bugfix: scan_test missing build apps without tests

See merge request espressif/esp-idf!12138
2021-01-28 17:48:24 +08:00
wangmengyang
51be1af028 add coexist hook functions and fix bugs for coexistence 2021-01-27 06:37:04 +00:00
Fu Hanxi
e4e375f488 fix: add spi_flash.h for s2, s3, c3 targets in cpu_start.c
update s2, s3, c3 ld files spi_flash_attach to esp_rom_spiflash_attach
2021-01-27 12:35:49 +08:00
Angus Gratton
fe8a891de9 Merge branch 'feature/support_esp32c3_master_cmake_secure_boot' into 'master'
bootloader/esp32c3: Support secure boot

Closes IDF-2115

See merge request espressif/esp-idf!11797
2021-01-21 08:42:49 +08:00
Li Shuai
27ddbf5fcc light sleep: libphy optimization for esp32c3 2021-01-20 13:28:30 +08:00
KonstantinKondrashov
98f726fa4b bootloader/esp32c3: Adds secure boot (not yet supported) 2021-01-19 20:51:13 +08:00
zwj
7c1c669799 component/bt: add BLE v5.0 feature for bluedroid host 2021-01-15 17:55:12 +08:00
Chen Jian Xing
5b44295cb9 esp_wifi: fix esp32c3 code issues
1. enable wifi clk and rm dport header
2.syn phy_init_data.h from esp32
2021-01-10 16:16:28 +08:00
Ivan Grokhotkov
b7b9ea4361 newlib: add _RETARGETABLE_LOCKING support
This adds support for the retargetable locking implementation in
newlib 3. This feature will be enabled in the future toolchain builds.
With the present version of the toolchain, this code doesn't get used.

When _RETARGETABLE_LOCKING gets enabled, newlib locking implementation
will be modified as follows:

- Legacy ESP-specific _lock_xxx functions are preserved. This is done
  because ROM copies of newlib in ESP32 and ESP32-S2 rely on these
  functions through the function pointer table. Also there is some
  code in IDF which still uses these locking functions.

- New __retarget_lock_xxx functions are introduced. Newlib expects
  these functions to be provided by the system. These functions work
  pretty much the same way as the ESP-specific _lock_xxx functions,
  except one major difference: _lock_acquire receives the lock pointer
  by value, and as such doesn't support lazy initialization.

- Static locks used by newlib are now explicitly initialized at
  startup. Since it is unlikely that these static locks are used at
  the same time, all compatible locks are set to point to the same
  mutex. This saves a bit of RAM. Note that there are still many locks
  not initialized statically, in particular those inside FILE
  structures.
2020-12-29 16:18:04 +01:00
Marius Vikhammer
4ff8c7ae98 esp_rom/esp_system: Add flag for ROM multiple UART output, esp32c3 console
From internal commit 6d894813
2020-12-24 14:18:01 +11:00
Angus Gratton
a5aac93051 esp_rom: Small changes for esp32c3 support
Updated from internal commit 6d894813
2020-12-24 13:40:01 +11:00
Angus Gratton
8929a9cdb1 Merge branch 'feature/aes_hal' into 'master'
AES: refactor and add HAL layer

See merge request espressif/esp-idf!10979
2020-12-11 15:39:49 +08:00
morris
c39476d699 esp_rom: added esp_rom_install_uart_printf 2020-12-11 11:45:10 +08:00
Marius Vikhammer
457ce080ae AES: refactor and add HAL layer
Refactor the AES driver and add HAL, LL and caps.

Add better support for running AES-GCM fully in hardware.
2020-12-10 09:04:47 +00:00
Angus Gratton
076be2b480 esp_rom: Refactor ROM CMakeLists.txt file
Reduce duplication and use a utility function for the "add ROM linker script"
pattern, move to a simple file structure of "one if block per target"
2020-11-30 15:23:15 +11:00
Angus Gratton
b68094199f esp_rom: Add initial ESP32-C3 support
From internal commit 7761d6e8
2020-11-30 11:12:56 +11:00
Cao Sen Miao
11188d2143 esp_flash:fix bug about clearing WLE automatically after actions 2020-11-12 16:44:29 +08:00
Angus Gratton
66fb5a29bb Whitespace: Automated whitespace fixes (large commit)
Apply the pre-commit hook whitespace fixes to all files in the repo.

(Line endings, blank lines at end of file, trailing whitespace)
2020-11-11 07:36:35 +00:00
weitianhua
1de3b17192 Fix BT controller dead issue caused by clk overflow 2020-10-29 10:49:30 +08:00
morris
9de6cba434 ci: add more build test for esp32-s3 2020-10-27 17:22:17 +08:00
Ivan Grokhotkov
48f27cb5ab Merge branch 'feature/esp32_ulp_allow_8kb' into 'master'
esp32: allow up to 8 kB of ULP program size

Closes IDFGH-1772

See merge request espressif/esp-idf!10727
2020-10-20 04:08:57 +08:00
Michael (XIAO Xufeng)
647dea9395 soc: combine xxx_caps.h into one soc_caps.h
During HAL layer refactoring and new chip bringup, we have several
caps.h for each part, to reduce the conflicts to minimum. But this is
The capabilities headers will be relataive stable once completely
written (maybe after the featues are supported by drivers).

Now ESP32 and ESP32-S2 drivers are relative stable, making it a good
time to combine all these caps.h into one soc_caps.h

This cleanup also move HAL config and pin config into separated files,
to make the responsibilities of these headers more clear. This is
helpful for the stabilities of soc_caps.h because we want to make it
public some day.
2020-10-17 16:10:15 +08:00
Marius Vikhammer
949fb8e63a SHA: add HAL layer and refactor driver
Add a LL and HAL layer for SHA.
2020-10-09 08:24:08 +00:00
Ivan Grokhotkov
ef10c2576f esp32: allow up to 8 kB of ULP program size
The remaining 4 kB had been reserved for storing RF calibration and
BT stack state since 4e092be6. However, these features never got
implemented. If we ever need to place RF related data into RTC slow
memory, we can do this by creating a variable with RTC_NOINIT_ATTR
instead.

Closes https://github.com/espressif/esp-idf/issues/3993
2020-10-05 11:41:39 +02:00
morris
61f89b97c6 bringup esp32-s3 on FPGA 2020-09-22 15:15:03 +08:00
chenjianqiang
f19cabb7e4 psram: support psram for esp32s3 2020-09-22 15:15:03 +08:00
morris
6225932201 bootloader_support: add esp32-s3 initial support 2020-09-22 15:15:03 +08:00
Jiang Jiang Jian
cfc4be0f06 Merge branch 'bugfix/confirmed_bugfix_from_baidu_proj' into 'master'
component_bt/bugfix: Confirmed bugfix from Baidu project

See merge request espressif/esp-idf!10450
2020-09-22 11:38:29 +08:00
Angus Gratton
033f49f974 Merge branch 'bugfix/cpp_header_rom_secure_boot' into 'master'
Secure Boot: Fixes the cpp macro in esp32 secure boot rom functions.

Closes IDFGH-3998

See merge request espressif/esp-idf!10528
2020-09-21 15:51:03 +08:00
Supreet Deshpande
0e940c80d4 Secure Boot: Fixes the cpp macro in esp32 secure boot rom functions.
Closes https://github.com/espressif/esp-idf/issues/5878
2020-09-20 22:50:44 +05:30
Michael (XIAO Xufeng)
fefdee1349 bootloader: fix the WRSR format for ISSI flash chips
1. The 2nd bootloader always call `rom_spiflash_unlock()`, but never help to clear the WEL bit when exit. This may cause system unstability.

   This commit helps to clear WEL when flash configuration is done.

   **RISK:** When the app starts, it didn't have to clear the WEL before it actually write/erase. But now the very first write/erase operation should be done after a WEL clear. Though the risk is little (all the following write/erase also need to clear the WEL), we still have to test this carefully, especially for those functions used by the OTA.

2. The `rom_spiflash_unlock()` function in the patch of ESP32 may (1) trigger the QPI, (2) clear the QE or (3) fail to unlock the ISSI chips.

   Status register bitmap of ISSI chip and GD chip:

| SR | ISSI | GD25LQ32C |
| -- | ---- | --------- |
| 0  | WIP  | WIP       |
| 1  | WEL  | WEL       |
| 2  | BP0  | BP0       |
| 3  | BP1  | BP1       |
| 4  | BP2  | BP2       |
| 5  | BP3  | BP3       |
| 6  | QE   | BP4       |
| 7  | SRWD | SRP0      |
| 8  |      | SRP1      |
| 9  |      | QE        |
| 10 |      | SUS2      |
| 11 |      | LB1       |
| 12 |      | LB2       |
| 13 |      | LB3       |
| 14 |      | CMP       |
| 15 |      | SUS1      |

   QE bit of other chips are at the bit 9 of the status register (i.e. bit 1 of SR2), which should be read by RDSR2 command.

   However, the RDSR2 (35H, Read Status 2) command for chip of other vendors happens to be the QIOEN (Enter QPI mode) command of ISSI chips. When the `rom_spiflash_unlock()` function trys to read SR2, it may trigger the QPI of ISSI chips.

   Moreover, when `rom_spiflash_unlock()` try to clear the BP4 bit in the status register, QE (bit 6) of ISSI chip may be cleared by accident. Or if the ISSI chip doesn't accept WRSR command with argument of two bytes (since it only have status register of one byte), it may fail to clear the other protect bits (BP0~BP3) as expected.

   This commit makes the `rom_spiflash_unlock()` check whether the vendor is issi. if so, `rom_spiflash_unlock()` only send RDSR to read the status register, send WRSR with only 1 byte argument, and also avoid clearing the QE bit (bit 6).

3. `rom_spiflash_unlock()` always send WRSR command to clear protection bits even when there is no protection bit active. And the execution of clearing status registers, which takes about 700us, will also happen even when there's no bits cleared.

   This commit skips the clearing of status register if there is no protection bits active.

Also move the execute_flash_command to be a bootloader API; move
implementation of spi_flash_wrap_set to the bootloader
2020-09-19 10:51:51 +08:00
weitianhua
c598b816ba Confirmed bugfix from Baidu project 2020-09-15 19:36:20 +08:00
Jakob Hasse
20c068ef3b cmock: added cmock as component
* changing dependencies from unity->cmock
* added component.mk and Makefile.projbuild
* ignore test dir in gen_esp_err_to_name.py
* added some brief introduction of CMock in IDF
2020-09-02 16:38:37 +08:00
Michael (XIAO Xufeng)
5425ef4ee4 hal: extract hal component from soc component 2020-09-01 13:25:32 +08:00
Renz Bagaporo
14902da344 esp32: move disabling rom log to esp_rom 2020-08-17 19:08:56 +08:00
Angus Gratton
a2dc60b254 Merge branch 'feature/secure_boot_esp32s2' into 'master'
Feature/secure boot esp32s2

See merge request espressif/esp-idf!8254
2020-07-28 16:39:34 +08:00
morris
2917651478 esp_rom: extract common ets apis into esp_rom_sys.h 2020-07-27 15:27:01 +08:00
Angus Gratton
a91bd4078f secure boot: Fixes for ESP32-S2 first boot logic 2020-07-27 00:01:10 +00:00