A problem if the Python interpreter used for idf.py (or set via PYTHON
variable) didn't match
"/usr/bin/env python" (or the associated executable for .py files, on
Windows).
Closes https://github.com/espressif/esp-idf/issues/3160
Possibly also fix for https://github.com/espressif/esp-idf/issues/2936
Adds build system test to catch any future direct execution of Python in
the standard build process.
Component which includes component_ulp_common.mk may also need to set
some of the same COMPONENT_XXX variables. Logically, we should combine
the lists of files to embed, ldflags, extra include dirs, etc.
Fixes https://github.com/espressif/esp-idf/issues/2157.
* Philosophical: "explicit is better than implicit".
* Practical: Allows useful errors if invalid directories given in components as the defaults aren't
always used. Also trims the -I path from a number of components that have no actual include
directory.
* Simplifies knowing which components will be header-only and which won't
When compiling
> const ulp_insn_t program[] = {
> I_DELAY(1)
> };
with the xtensa-esp32-elf-g++ compiler i always got the error:
> sorry, unimplemented: non-trivial designated initializers not supported
>
> };
This was due to the different order in the macro and the struct. The struct has another order of the fields (opcode, unused, cycles) vs (cycles, unused, opcode):
> struct {
> uint32_t cycles : 16; /*!< Number of cycles to sleep */
> uint32_t unused : 12; /*!< Unused */
> uint32_t opcode : 4; /*!< Opcode (OPCODE_DELAY) */
> } delay; /*!< Format of DELAY instruction */
After updating the order in the macro it is possible to compile with the g++ compiler.
Merges https://github.com/espressif/esp-idf/pull/1310
- RTC_CNTL_SLOWCLK_FREQ define is removed; rtc_clk_slow_freq_get_hz
function can be used instead to get an approximate RTC_SLOW_CLK
frequency
- Clock calibration is performed at startup. The value is saved and used
for timekeeping and when entering deep sleep.
- When using the 32k XTAL, startup code will wait for the oscillator to
start up. This can be possibly optimized by starting a separate task
to wait for oscillator startup, and performing clock switch in that
task.
- Fix a bug that 32k XTAL would be disabled in rtc_clk_init.
- Fix a rounding error in rtc_clk_cal, which caused systematic frequency
error.
- Fix an overflow bug which caused rtc_clk_cal to timeout early if the
slow_clk_cycles argument would exceed certain value
- Improve 32k XTAL oscillator startup time by introducing bootstrapping
code, which uses internal pullup/pulldown resistors on 32K_N/32K_P
pins to set better initial conditions for the oscillator.
This fixes incorrect descriptions of I_END/I_SLEEP instructions and
changes the definition of I_END. New instruction, I_WAKE, is added,
which wakes up the SoC. Macro for ADC instruction is defined, and new
tests are added.
- I_RD_REG used the wrong union member (.rd_reg) due to a copy-paste
mistake
- Peripheral register address in bits[7:0] should be given in words,
not in bytes
Fixes https://github.com/espressif/esp-idf/issues/297
