8 Commits

Author	SHA1	Message	Date
Marius Vikhammer	22091c8744	feat(wdt): add multicore support for WDTs on RISCV	2023-10-23 18:26:08 +08:00
Omar Chebib	8ca191e4c1	fix(esp32p4): Fixed interrupt handling to use the CLIC controller	2023-08-31 12:16:08 +08:00
Armando	ecf1461f1c	feat(panic): base support on p4	2023-07-25 05:59:10 +00:00
Alexey Lapshin	4df3ff619e	feat(esp_system): implement hw stack guard for riscv chips ... - add hardware stack guard based on assist-debug module - enable hardware stack guard by default - disable hardware stack guard for freertos ci.release test - refactor rtos_int_enter/rtos_int_exit to change SP register inside them - fix panic_reason.h header for RISC-V - update docs to include information about the new feature	2023-07-01 16:27:40 +00:00
Ivan Grokhotkov	336d0b64de	riscv: fix panic_reasons being an instance of enum, not type name	2022-01-27 11:00:09 +07:00
Martin Vychodil	69096ddce5	Security: ESP32C3 memory protection feature (IRAM0/DRAM0) ... Software support for PMS module. Allows controlled memory access to IRAM (R/W/X) and DRAM0 (R/W) On/locked by default, configurable in Kconfig (esp_system) Closes https://jira.espressif.com:8443/browse/IDF-2092	2021-01-27 08:44:03 +01:00
Omar Chebib	c218f669ba	panic on RISC-V: Take into account Merge Request comments	2020-12-31 15:46:17 +08:00
Renz Bagaporo	4cc6b5571b	esp_system: support riscv panic	2020-11-13 07:49:11 +11:00