4 Commits

Author	SHA1	Message	Date
Marius Vikhammer	477844806e	re-enable riscv ulp gpio support and examples	2022-06-27 17:17:06 +08:00
Sudeep Mohanty	b72f987c5c	ulp: Added ULP RISC-V support for esp32s3 ... This commit adds support for ULP RISC-V for esp32s3. Signed-off-by: Sudeep Mohanty <sudeep.mohanty@espressif.com>	2022-06-22 13:33:14 +08:00
Jakob Hasse	81e9266204	[examples]: removed hyphens ... Replaced hyphens with underscores in examples project definition for all examples which had hyphens in their project name. dpp-enrollee is an exceptions because the name matches the project directory name while the project directory also contains hyphens.	2021-10-09 13:58:24 +08:00
Marius Vikhammer	386739595f	RISCV-ULP: Add DS18B20 1wire RISCV-ULP example	2021-06-25 11:26:39 +08:00