3 Commits

Author SHA1 Message Date
intern
74d745a80b docs: update cn trans for upl docs 2022-06-29 11:56:59 +08:00
Sudeep Mohanty
b72f987c5c ulp: Added ULP RISC-V support for esp32s3
This commit adds support for ULP RISC-V for esp32s3.

Signed-off-by: Sudeep Mohanty <sudeep.mohanty@espressif.com>
2022-06-22 13:33:14 +08:00
morris
61f89b97c6 bringup esp32-s3 on FPGA 2020-09-22 15:15:03 +08:00