update ld and heap region
Divide origin fpga ld to several lds, choose specific ld for normal/BT/Trace by menuconfig, change iram/dram len in ld to full use hardware ram region.
See merge request !28
This is a workaround for a hardware bug with cache initialization.
Only two lines of code related to DPORT_APP_CACHE_MMU_IA_CLR were added around mmu_init(1); call,
and two lines at the end of comment block.
I reformatted surrounding lines to use spaces for indentation, like the rest of the code in this file does.
