Commit Graph

36 Commits

Author SHA1 Message Date
Cao Sen Miao
f28f75a46b spi_flash: Add several flash chips HPM(120M) support 2022-09-30 11:15:34 +08:00
Cao Sen Miao
67b4ba33dd spi_flash: add support for th 1M flash 2022-01-10 12:39:09 +08:00
Cao Sen Miao
6c0aebe279 esp_flash: add opi flash support in esp_flash chip driver, for MXIC 2021-09-07 14:44:40 +08:00
Michael (XIAO Xufeng)
26585b4b4b esp_flash: support override default chip driver list 2021-04-26 16:05:42 +08:00
Cao Sen Miao
c54ea54d98 spi_flash: make suspend off by default and add more information for using suspend 2021-03-26 13:57:14 +08:00
Michael (XIAO Xufeng)
a0573f5b9f spi_flash: make the auto_suspend default y on C3 2021-02-04 14:11:04 +08:00
Mahavir Jain
e712a91488 spi_flash: add config option to enable encrypted partition read/write
This feature can be disabled to save some IRAM (approx 1KB) for cases
where flash encryption feature is not required.
2021-01-28 12:19:21 +00:00
Cao Sen Miao
f3e79ca166 spi_flash(c3): add boya chip support for suspend feature 2021-01-25 11:14:06 +08:00
Cao Sen Miao
9905da46e0 spi_flash: Add auto suspend mode on esp32c3 2021-01-25 11:14:02 +08:00
KonstantinKondrashov
afef16c2e9 spi_flash: Support suspend/resume mode for operations
- Adds arbitration between the erase and write in suspend mode
     (If the flash memory is suspended then only a read operation can be performed.)
- espcoredump: Dump does not use suspend feature, just resume before continue.
- spi_flash: Add release_cpu() to do suspend/release_cpu/resume
2021-01-25 11:13:38 +08:00
Ivan Grokhotkov
7f3b16a99d freertos: always enable static allocation
to use it for newlib locks
2020-12-29 16:18:04 +01:00
Angus Gratton
d4c9a45675 spi_flash: Add ESP32-C3 support
Based on internal commit 3ef01301fff
2020-12-17 15:34:13 +11:00
Michael (XIAO Xufeng)
3bacf35310 esp_flash: support high capacity flash chips (32-bit address) 2020-10-29 18:20:11 +08:00
Cao Sen Miao
b9f6efd99a esp_flash: change timeout threshold and can close timeout 2020-10-12 10:43:25 +08:00
Michael (XIAO Xufeng)
fefdee1349 bootloader: fix the WRSR format for ISSI flash chips
1. The 2nd bootloader always call `rom_spiflash_unlock()`, but never help to clear the WEL bit when exit. This may cause system unstability.

   This commit helps to clear WEL when flash configuration is done.

   **RISK:** When the app starts, it didn't have to clear the WEL before it actually write/erase. But now the very first write/erase operation should be done after a WEL clear. Though the risk is little (all the following write/erase also need to clear the WEL), we still have to test this carefully, especially for those functions used by the OTA.

2. The `rom_spiflash_unlock()` function in the patch of ESP32 may (1) trigger the QPI, (2) clear the QE or (3) fail to unlock the ISSI chips.

   Status register bitmap of ISSI chip and GD chip:

| SR | ISSI | GD25LQ32C |
| -- | ---- | --------- |
| 0  | WIP  | WIP       |
| 1  | WEL  | WEL       |
| 2  | BP0  | BP0       |
| 3  | BP1  | BP1       |
| 4  | BP2  | BP2       |
| 5  | BP3  | BP3       |
| 6  | QE   | BP4       |
| 7  | SRWD | SRP0      |
| 8  |      | SRP1      |
| 9  |      | QE        |
| 10 |      | SUS2      |
| 11 |      | LB1       |
| 12 |      | LB2       |
| 13 |      | LB3       |
| 14 |      | CMP       |
| 15 |      | SUS1      |

   QE bit of other chips are at the bit 9 of the status register (i.e. bit 1 of SR2), which should be read by RDSR2 command.

   However, the RDSR2 (35H, Read Status 2) command for chip of other vendors happens to be the QIOEN (Enter QPI mode) command of ISSI chips. When the `rom_spiflash_unlock()` function trys to read SR2, it may trigger the QPI of ISSI chips.

   Moreover, when `rom_spiflash_unlock()` try to clear the BP4 bit in the status register, QE (bit 6) of ISSI chip may be cleared by accident. Or if the ISSI chip doesn't accept WRSR command with argument of two bytes (since it only have status register of one byte), it may fail to clear the other protect bits (BP0~BP3) as expected.

   This commit makes the `rom_spiflash_unlock()` check whether the vendor is issi. if so, `rom_spiflash_unlock()` only send RDSR to read the status register, send WRSR with only 1 byte argument, and also avoid clearing the QE bit (bit 6).

3. `rom_spiflash_unlock()` always send WRSR command to clear protection bits even when there is no protection bit active. And the execution of clearing status registers, which takes about 700us, will also happen even when there's no bits cleared.

   This commit skips the clearing of status register if there is no protection bits active.

Also move the execute_flash_command to be a bootloader API; move
implementation of spi_flash_wrap_set to the bootloader
2020-09-19 10:51:51 +08:00
Michael (XIAO Xufeng)
37423083bb spi_flash: add config option to override flash size in bootloader header
Sometimes the flash size read from bootloader is not correct. This may
forbid SPI Flash driver from reading the the area larger than the size
in bootloader header.

When the new config option is enabled, the latest configured
ESPTOOLPY_FLAHSIZE in the app header will be used to override the value
read from bootloader header.
2020-09-02 00:35:53 +08:00
Mahavir Jain
05da91f0db spi_flash: add configuration option to select flash write chunk size
Flash write operation is broken down into smaller chunk writes. Size
of this chunk was previously set to 8K but that in-turn meant cache and
non-IRAM resident interrupts could stay disabled upto ~24msec for 8K flash
write operation. If chunk size is brought down to 256 (typical flash page size)
then it brings down cache and non-IRAM interrupts disable duration to ~1msec.

Fix here keeps defaults same but provides configuration option to tweak the
setting based on application requirement.
2020-06-05 14:45:41 +05:30
KonstantinKondrashov
304f67e42a spi_flash(LEGACY_IMPL): Add a Kconfig option - Bypass a block erase and always do sector erase
Closes: IDF-1561
2020-04-30 13:58:13 +08:00
KonstantinKondrashov
3cb655eaab spi_flash(LEGACY_IMPL): Add vTaskDelay while a long erasing
Added Kconfig options to enable yield operation during flash erase

Closes: https://github.com/espressif/esp-idf/issues/2083
Closes: https://github.com/espressif/esp-idf/issues/4916
Closes: IDFGH-261
2020-04-30 13:58:13 +08:00
michael
fdf983e0c4 spi: fix config break and reduce overhead of the bus lock on SPI1
The SPI bus lock on SPI1 introduces two side effects:

1. The device lock for the main flash requires the
`CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION` to be selected, however this
option is disabled by default in earlier IDF versions. Some developers
may find their project cannot be built by their old sdkconfig files.

2. Usually we don't need the lock on the SPI1 bus, due to it's
restrictions. However the overhead still exists in this case, the IRAM
cost for static version of semaphore functions, and the time cost when
getting and releasing the lock.

This commit:

1. Add a CONFIG_SPI_FLASH_BYPASS_MAIN_LOCK option, which will forbid the
space cost, as well as the initialization of the main bus lock.

2. When the option is not selected, the bus lock is used, the
`CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION` will be selected explicitly.

3. Revert default value of `CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION`
to `n`.

introduced in 49a48644e4.

Closes https://github.com/espressif/esp-idf/issues/5046
2020-04-22 16:06:13 +08:00
Michael (XIAO Xufeng)
3b429766bc esp_flash: support MXIC flash chips
The default chip driver (chip_generic) use command 01H + 2 bytes to
clear the QE bit. However this will accidently change the configuration
register value of the MXIC chip.

MXIC chip driver is added to fix that.
2020-04-01 20:54:23 +08:00
Renz Christian Bagaporo
e6ad330018 ble_mesh_wifi_coexist example: Disable Wi-Fi RX IRAM optimisation
Otherwise IRAM usage is too high in this example.
2019-11-28 09:20:00 +08:00
Angus Gratton
8675a818f9 Merge branch 'master' into feature/esp32s2beta_merge 2019-10-22 13:51:49 +11:00
Michael (XIAO Xufeng)
eb104aa16f esp_flash: fix the quad issue for some GD flash chips
The GD flash with product ID 40H, is already used in Wrover-nosufix modules.
2019-10-14 17:25:59 +08:00
Angus Gratton
309376f51a spi_flash: Force legacy mode for ESP32-S2
Can be removed once IDF-763 is merged
2019-08-13 17:14:16 +10:00
Michael (XIAO Xufeng)
1036a091fe spi_flash: support working on differnt buses and frequency 2019-06-18 06:32:52 +00:00
Roland Dobai
22d070e0af spi_flash: Rename long Kconfig options 2019-06-12 08:03:07 +02:00
Roland Dobai
842384a0d3 spi_flash: Fix Kconfig indentation
Closes https://github.com/espressif/esp-idf/issues/3598
2019-06-12 08:03:07 +02:00
Roland Dobai
37126d3451 Correct Kconfigs according to the coding style 2019-01-29 13:37:01 +01:00
Angus Gratton
f7ac41c2da spi_flash: Add option to log warnings if (spuriously) writing zero bits to ones
Won't work for SPIFFS, maybe some other implementations?
2017-12-04 09:55:05 +11:00
Angus Gratton
892b3ff14b spi_flash: Add option to verify all writes by reading back data
Helpful when debugging SPI flash hardware related issues.

TW15203
2017-12-04 09:55:05 +11:00
Angus Gratton
670733df9f spi_flash: Abort on writes to dangerous regions (bootloader, partition table, app)
Can be disabled or made into a failure result in kconfig if needed.
2017-11-03 15:52:27 -07:00
Ivan Grokhotkov
fb43948413 Update several Kconfig files to make help texts compatible with ReST 2017-08-22 14:34:19 +08:00
Alexey Gerenkov
0860f46220 spi_flash: Fixed bug in SPI flash ROM driver to work with embedded flash chip
1) fixed SPI_read_status: added check for flash busy flag in matrix mode
2) fixed SPI_page_program: enable write before writing data to SPI FIFO
3) SPI flash ROM funcs replacement is controlled via menuconfig option
2017-04-11 10:51:19 +08:00
Wu Jian Gang
ed0a85ab4d Kconfig: use 4 spaces to instead 1 tab
In some Kconfig file, both 4 spaces and 1 tab are used mix, let's just
use 4 space, it will be clean in some editor.
2016-09-28 13:24:58 +08:00
Ivan Grokhotkov
f2149eabee components/spi_flash: add flash operation counters option to Kconfig 2016-09-23 08:44:45 +08:00