Commit Graph

25 Commits

Author SHA1 Message Date
liuning
27e3d41026 fix(clk): clear all lpclk source at clk init 2024-02-22 15:07:59 +08:00
morris
71cf16ec01 feat(gptimer): use RCC atomic block to enable/reset peripheral 2023-08-22 17:05:35 +08:00
Gustavo Henrique Nihei
3cbac3dd1d esp_system: Ensure TIMG0 clock is always enabled during normal operation
If the TimerGroup 0 clock is disabled and then reenabled, the watchdog
registers (Flashboot protection included) will be re-enabled, and some
seconds later, will trigger an unintended reset.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2023-03-06 04:58:11 +00:00
Li Shuai
526a9c665a backup dma: force clear reset signal to fix the backup dma operation failure caused by RTC_SW_CPU_RST 2022-10-20 03:24:49 +00:00
jingli
60c1811433 esp_hw_support/clk_cali: remove redundant check for cali value 2022-09-21 03:03:25 +00:00
Guillaume Souchere
6005cc9163 hal: Deprecate interrupt_controller_hal.h, cpu_hal.h and cpu_ll.h interfaces
This commit marks all functions in interrupt_controller_hal.h, cpu_ll.h and cpu_hal.h as deprecated.
Users should use functions from esp_cpu.h instead.
2022-07-22 00:06:06 +08:00
wangmengyang
1d55f12c2d component/bt: reset Bluetooth hardware during controller inititalization on ESP32-C3/ESP32-S3
1. Rename MACROs SYSTEM_WIFI_RST_EN register bit fields to be more recognizable
2. reset Bluetooth baseband and clock bits to fix the issue of task watchdog triggered during controller initialization due to invalid hardware state
2022-07-06 16:23:48 +08:00
songruojing
03477a59db rtc_clk: Fix rtc8m calibration failure after cpu/core reset
1. make sure 8md256 clk is enabled before calibration
2. improve bootloader and application startup 8m, 8md256 enable logic
2022-06-13 17:47:51 +08:00
KonstantinKondrashov
ac4c7d99fe dport: Move DPORT workaround to G0 2022-05-31 13:44:18 +08:00
songruojing
a5b09cf015 rtc_clk: Clean up some clock related enum and macro in soc/rtc.h, replace with new ones in
soc/clk_tree_defs.h
2022-05-24 22:59:41 +08:00
Marius Vikhammer
d2872095f9 soc: moved kconfig options out of the target component.
Moved the following kconfig options out of the target component:
 * CONFIG_ESP*_DEFAULT_CPU_FREQ* -> esp_system
 * ESP*_REV_MIN -> esp_hw_support
 * ESP*_TIME_SYSCALL -> newlib
 * ESP*_RTC_* -> esp_hw_support

Where applicable these target specific konfig names were merged into
a single common config, e.g;
CONFIG_ESP*_DEFAULT_CPU_FREQ -> CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ
2022-04-21 12:09:43 +08:00
Ivan Grokhotkov
c70a69b1dd Merge branch 'bugfix/remove_ref_non_ex_options' into 'master'
config: removed references to non-existing kconfig options

See merge request espressif/esp-idf!17495
2022-03-25 18:02:54 +08:00
Marius Vikhammer
0fbae992dd config: removed references to non-existing kconfig options 2022-03-15 18:32:22 +08:00
Marius Vikhammer
ca3c056ac9 kconfig: replace deprecated options with new values 2022-03-15 16:28:53 +08:00
songruojing
c1dedb33fa esp_system: replace the range comparsion for reset reason in perip clk init with specific reset reason check, also add a test case in LEDC to check for the perip clk not being disabled after cpu reset 2022-02-09 15:54:34 +08:00
Cao Sen Miao
eddc196081 esp_clk: refactor target/clk.h to private/esp_clk.h 2021-11-26 14:56:30 +08:00
morris
16677b0d3c global: make periph enable/disable APIs private
peripheral enable/disable usually should be managed by driver itself,
so make it as espressif private APIs, not recommended for user to use it
in application code.
However, if user want to re-write the driver or ports to other platform,
this is still possible by including the header in this way:
"esp_private/peripheral_ctrl.h"
2021-11-08 10:37:47 +08:00
Armando
c45c6f52f1 adc: support adc efuse-based calibration on esp32s3 2021-09-14 11:42:50 +08:00
Li Shuai
366d0a724a light sleep: set wifi light sleep clock source to rtc slow clock 2021-08-04 21:31:47 +08:00
morris
1560d6f1ba soc: add reset reasons in soc component 2021-07-13 10:45:38 +08:00
KonstantinKondrashov
aa1338bf23 wdt: Fix timeout and RTC_SLOW_CLK
RTC_SLOW_CLK
ESP32:    150kHz
ESP32-S2:  90kHz
ESP32-S3: 150kHz
ESP32-C3: 150kHz
2021-03-19 00:15:18 +08:00
Angus Gratton
d6f4d99d93 core system: Fix warnings in compilation when assertions are disabled
Adds a CI config for hello world that sets this, to catch future regressions
2021-03-03 10:26:57 +11:00
Chen Jian Xing
f71adec8fb Support ESP32S3 (beta2) WiFi 2021-01-25 00:18:42 +08:00
KonstantinKondrashov
dada7cd035 global: Uses CCOUNT API instead of XTHAL macro 2021-01-12 16:24:23 +08:00
Renz Bagaporo
4cc6b5571b esp_system: support riscv panic 2020-11-13 07:49:11 +11:00