8 Commits

Author	SHA1	Message	Date
laokaiyao	951bdd70a2	fix(ci): fix the readme check of c5 mp	2024-07-30 15:40:19 +08:00
Michael (XIAO Xufeng)	f251e32f48	feat(uart_test): add test case for uart tx blocked by auto-suspend	2024-04-05 03:01:24 +08:00
LiPeng	235bb6f294	fix(uart): Fixed issue that TX be blocked by auto-lightsleep	2024-04-05 03:01:24 +08:00
Song Ruo Jing	5276cd4f1d	refactor(uart): add support to be able to test LP_UART port ... Increase LP_UART_EMPTY_THRESH_DEFAULT value to 4. The original value could cause the FIFO become empty before filling next data into the FIFO when the buadrate is high. TX_DONE interrupt would raise before actual transmission complete in such case.	2024-02-07 14:37:48 +08:00
Armando	3c5a4f9e8a	ci(p4): added todo jira for disabled tests on p4	2024-01-04 09:36:38 +08:00
Armando	907b876354	ci(p4): temporarily disable failed ci tests on p4	2024-01-04 09:36:06 +08:00
Song Ruo Jing	ef281dff5a	fix(esp_driver_uart): always use heap_caps_malloc to malloc memory base on flags	2023-12-15 17:03:58 +08:00
Song Ruo Jing	6ad80f0332	refactor(uart): make uart driver as component, and fix astyle	2023-12-15 17:03:51 +08:00