Commit Graph

10 Commits

Author SHA1 Message Date
Kampi
5d9ddd4c1d bugfix: Change namespace variable to nvs_namespace (C++ compatibility)
Closes https://github.com/espressif/esp-idf/pull/11028
2023-03-24 11:39:13 +08:00
Marius Vikhammer
55879e36ab system: fix printf format errors in all system and cxx examples 2022-12-12 12:55:02 +08:00
Sudeep Mohanty
a28791dbed ulp: fix incorrect bit-width operator while reading RTC_CNTL_LOW_POWER_ST_REG during wakeup
This commit fixes a bug wherein an incorrect bit-width of 0 was being
used while reading the RTC_CNTL_LOW_POWER_ST_REG in ulp_fsm example code
while judging whether the system is ready for wakeup. The correct value
should be a bit-width of 1 to read bit#27 (RTC_CNTL_MAIN_STATE_IDLE) of
the RTC_CNTL_LOW_POWER_ST_REG register on esp32.
2022-10-17 10:59:26 +02:00
Sudeep Mohanty
afbea0a04c ulp: Updated ULP docs and ulp_fsm example for wakeup when SoC is not in sleep mode.
This commit updates the ULP documentation and the ulp_fsm example with
the scenario when a wakeup is triggered from the ULP coproc when the
main CPU is not in sleep mode.

Closes https://github.com/espressif/esp-idf/issues/8341
Closes https://github.com/espressif/esp-idf/issues/5254
2022-09-06 10:32:05 +02:00
Ivan Grokhotkov
e596c84d49 build system: re-add -Wno-format as private flag for some example components 2022-08-03 16:42:47 +04:00
Marius Vikhammer
797358f953 ulp-fsm: support ulp-fsm example on S3 2022-06-13 13:58:29 +08:00
Omar Chebib
2571aaf3c9 G0: target component (components/esp32*) doesn't depend on driver anymore 2022-03-02 04:21:00 +00:00
Sudeep Mohanty
4d8a0cce29 ulp: Added support for ULP FSM on esp32s3 and fixed bugs for esp32s2
This commit enables ULP FSM support for esp32s3 and updates ULP FSM code
flow for other chips.
It adds C Macro support for the ULP FSM instruction set on esp32s2 and
esp32s3.
The unit tests are also updated to test ULP FSM on ep32s2 and esp32s3.
2022-02-22 12:25:57 +05:30
Roland Dobai
766aa57084 Build & config: Remove leftover files from the unsupported "make" build system 2021-11-11 15:32:36 +01:00
Marius Vikhammer
386739595f RISCV-ULP: Add DS18B20 1wire RISCV-ULP example 2021-06-25 11:26:39 +08:00