8 Commits

Author	SHA1	Message	Date
Sudeep Mohanty	96b152a01f	ulp-riscv: ULP RISC-V I2C example gets stuck on esp32s2 ... This commit fixes an issue where in the ULP RISC-V I2C example causes a spurious wakeup of the main CPU because of a Trap signal when the ULP core does not meet the wakeup threshold values. This was due to the fact that the RTC_CNTL_COCPU_DONE signal was being set before the RTC_CNTL_COCPU_SHUT_RESET_EN signal which was causing the the ULP RISC-V core to not reset properly on each cycle. Closes https://github.com/espressif/esp-idf/issues/10301	2023-01-02 14:24:16 +01:00
Marius Vikhammer	4acfe1a91a	ulp-riscv: always force COCPU clock on S3 ... The coprocessor cpu trap signal doesnt have a stable reset value, force ULP-RISC-V clock on to stop RTC_COCPU_TRAP_TRIG_EN from waking the CPU	2022-10-25 13:51:04 +08:00
Sudeep Mohanty	b72f987c5c	ulp: Added ULP RISC-V support for esp32s3 ... This commit adds support for ULP RISC-V for esp32s3. Signed-off-by: Sudeep Mohanty <sudeep.mohanty@espressif.com>	2022-06-22 13:33:14 +08:00
Marius Vikhammer	386739595f	RISCV-ULP: Add DS18B20 1wire RISCV-ULP example	2021-06-25 11:26:39 +08:00
Renz Bagaporo	19d8a403e6	ulp: set riscv-ulp as done signal source properly ... Closes https://github.com/espressif/esp-idf/issues/6069	2021-01-22 15:22:01 +08:00
Angus Gratton	66fb5a29bb	Whitespace: Automated whitespace fixes (large commit) ... Apply the pre-commit hook whitespace fixes to all files in the repo. (Line endings, blank lines at end of file, trailing whitespace)	2020-11-11 07:36:35 +00:00
morris	2917651478	esp_rom: extract common ets apis into esp_rom_sys.h	2020-07-27 15:27:01 +08:00
Felipe Neves	b6dba84323	ulp: added support to building code for riscv ULP coprocessor	2020-07-15 15:28:49 -03:00