Small changes to clock calibration value will cause increasing errors
the longer the device runs. Consider the case of deep sleep, assuming
that RTC counter is used for timekeeping:
- before sleep:
time_before = rtc_counter * calibration_val
- after sleep:
time_after = (rtc_counter + sleep_count) * (calibration_val + epsilon)
where 'epsilon' is a small estimation error of 'calibration_val'.
The apparent sleep duration thus will be:
time_after - time_before = sleep_count * (calibration_val + epsilon)
+ rtc_counter * epsilon
Second term on the right hand side is the error in time difference
estimation, it is proportional to the total system runtime (rtc_counter).
To avoid this issue, this change makes RTC_SLOW_CLK calibration value
persistent across restarts. This allows the calibration value update to
be preformed, while keeping time after update same as before the update.
This change removes the erroneous cast to uint32_t (which caused time to
wrap around after 1 hour) and splits the multiplication into two terms
to remove the wraparound after 13 days.
Ref. https://esp32.com/viewtopic.php?f=13&t=1908
- RTC_CNTL_SLOWCLK_FREQ define is removed; rtc_clk_slow_freq_get_hz
function can be used instead to get an approximate RTC_SLOW_CLK
frequency
- Clock calibration is performed at startup. The value is saved and used
for timekeeping and when entering deep sleep.
- When using the 32k XTAL, startup code will wait for the oscillator to
start up. This can be possibly optimized by starting a separate task
to wait for oscillator startup, and performing clock switch in that
task.
- Fix a bug that 32k XTAL would be disabled in rtc_clk_init.
- Fix a rounding error in rtc_clk_cal, which caused systematic frequency
error.
- Fix an overflow bug which caused rtc_clk_cal to timeout early if the
slow_clk_cycles argument would exceed certain value
- Improve 32k XTAL oscillator startup time by introducing bootstrapping
code, which uses internal pullup/pulldown resistors on 32K_N/32K_P
pins to set better initial conditions for the oscillator.
While there was no register at DR_REG_FRC_TIMER_BASE + 0x60, due to
peripheral address space wraparound this write actually affected one of
FRC2 registers, which is used by WiFi stack to implement legacy
ets_timer APIs.
This change uses FRC_TIMER_LOAD_REG(0) instead, which can be set to
known value safely.
In some cases (when RTC register reads are performed from the APP CPU), a write to FRC_TIMER_INT_REG may be lost on the bus.
Writing to another DPORT register immediately before or after that works around the issue.
We write one dummy value to an address which doesn’t have any register associated with it.
Fixes https://github.com/espressif/arduino-esp32/issues/120
Fixes for github issues
This MR contains a bunch of small fixes for issues raised on Github and esp32.com forum:
- vfs doesn't check error code returned by open syscall
- spi_flash doesn't work when built in release mode
- duplicate definition of O_NONBLOCK when combining LwIP socket.h with sys/fcntl.h
- wrong order of creation of standard streams
- `_times_r` returning incorrect values, causing `clock`to return double of the actual time
- driver/gpio.h: comment fix
- wifi event handlers: fix incorrect MAC address printed by logging statements
- move some functions out of IRAM when compiling for bootloader
Please check commit descriptions for links to issues/forum posts and more details.
See merge request !183
- spaces->tabs in tasks.c
- update vfs_uart.c to use per-UART locks
- add license to vfs_uart.c
- allocate separate streams for stdout, stdin, stderr, so that they can be independently reassigned
- fix build system test failure
