3 Commits

Author	SHA1	Message	Date
Angus Gratton	420aef1ffe	Updates for riscv support ... * Target components pull in xtensa component directly * Use CPU HAL where applicable * Remove unnecessary xtensa headers * Compilation changes necessary to support non-xtensa gcc types (ie int32_t/uint32_t is no longer signed/unsigned int). Changes come from internal branch commit a6723fc	2020-11-13 07:49:11 +11:00
Angus Gratton	66fb5a29bb	Whitespace: Automated whitespace fixes (large commit) ... Apply the pre-commit hook whitespace fixes to all files in the repo. (Line endings, blank lines at end of file, trailing whitespace)	2020-11-11 07:36:35 +00:00
Felipe Neves	2e826b7a8f	intr_alloc: split interrupt allocator into common-code and platform-code ... esp_system: removed repeated interrupt allocator code and moved common code to esp_system xtens: moved xtensa specific code from freertos to the xtensa component hal/interrupt_controller: added interrupt controller hal and ll files docs: update the doxyfile with new location of esp_itr_alloc.h file xtensa: fixed dangerous relocation problem after moving xtensa interrupt files out of freertos docs: removed Xtensa reference from intr_allocator api-reference xtensa: pushed the interrupt function that manages non iram interrupts to the xtensa layer esp_system/test: fixed platform dependent setting for intr_allocator tests hal: rename the functions used to manage non iram interrupt mask.	2020-09-30 07:44:12 +08:00