54 Commits

Author	SHA1	Message	Date
Marius Vikhammer	386739595f	RISCV-ULP: Add DS18B20 1wire RISCV-ULP example	2021-06-25 11:26:39 +08:00
Angus Gratton	3ee4370578	esp32s2 riscv ulp: Ensure reset vector is always at offset 0x0 ... Previous linker script relied on nothing else using the .text section As reported at https://esp32.com/viewtopic.php?f=2&t=20734&p=75997	2021-05-06 09:25:32 +10:00
Angus Gratton	66fb5a29bb	Whitespace: Automated whitespace fixes (large commit) ... Apply the pre-commit hook whitespace fixes to all files in the repo. (Line endings, blank lines at end of file, trailing whitespace)	2020-11-11 07:36:35 +00:00
Felipe Neves	b6dba84323	ulp: added support to building code for riscv ULP coprocessor	2020-07-15 15:28:49 -03:00