The riscv vectors.S in riscv component contains the trap vector, which is responsible to
defer interrupts and examine if a task context switch is needed, this change cleans up
this code by hiding all freertos details behind on two functions rtos_it_enter/exit and
their implementations are placed in freertos riscv port files.
SoC level exceptions such as watchdog timer and cache errors are now supported.
Such exceptions now triggers a panic, giving more information about how
and when it happened.
