4 Commits

Author	SHA1	Message	Date
Omar Chebib	a8b1475fe7	feat(riscv): implement coprocessors save area and FPU support ... This commit mainly targets the ESP32-P4. It adds supports for coprocessors on RISC-V based targets. The coprocessor save area, describing the used coprocessors is stored at the end of the stack of each task (highest address) whereas each coprocessor save area is allocated at the beginning of the task (lowest address). The context of each coprocessor is saved lazily, by the task that want to use it.	2023-10-23 11:10:28 +08:00
Omar Chebib	8ca191e4c1	fix(esp32p4): Fixed interrupt handling to use the CLIC controller	2023-08-31 12:16:08 +08:00
Alexey Lapshin	4df3ff619e	feat(esp_system): implement hw stack guard for riscv chips ... - add hardware stack guard based on assist-debug module - enable hardware stack guard by default - disable hardware stack guard for freertos ci.release test - refactor rtos_int_enter/rtos_int_exit to change SP register inside them - fix panic_reason.h header for RISC-V - update docs to include information about the new feature	2023-07-01 16:27:40 +00:00
Sudeep Mohanty	8fd953c627	freertos-smp: add support for RISC-V targets oon FreeRTOS SMP ... TBD: Initial commit. Enables risc-v port.	2022-06-13 13:34:21 +02:00