VDD_SDIO power domain can now be configured for light sleep
by the application. It is now possible to keep the power domain
ON during light sleep, keeping the GPIOs connected to it powered.
The power domain will, by default be:
- Kept ON if CONFIG_ESP_SYSTEM_PD_FLASH is not set
- Turned OFF if not set
The application can still force it to be ON by calling
`esp_sleep_pd_config(ESP_PD_DOMAIN_VDDSDIO, ESP_PD_OPTION_ON);`
On S2 the brown out detector would occasionally trigger erroneously during deep sleep.
Disable it before sleeping to circumvent this issue.
Closes https://github.com/espressif/esp-idf/issues/6179
components/bt: Do not use feature: timer support isr dispatch method
disable controller after wake up finished.
protect critical section of power down
choose clk in sleep
components/coex: mac bb power down in light sleep
components/coex: Macro changed
components/os: protect reserved interrupt number
update phy to phy_version 300,6e46ba7,Jan 25 2021
some bugfix
ESP32 in revision0 and revision1 uses touchpad to provide
current to oscillate xtal 32k. But revision2 and revision3
do not need to do that.
Note: touchpad can not work and toupad/ULP wakeup sources
are not available when toupad provides current to xtal 32k
During HAL layer refactoring and new chip bringup, we have several
caps.h for each part, to reduce the conflicts to minimum. But this is
The capabilities headers will be relataive stable once completely
written (maybe after the featues are supported by drivers).
Now ESP32 and ESP32-S2 drivers are relative stable, making it a good
time to combine all these caps.h into one soc_caps.h
This cleanup also move HAL config and pin config into separated files,
to make the responsibilities of these headers more clear. This is
helpful for the stabilities of soc_caps.h because we want to make it
public some day.
Fix for issues where RTC FAST memory is updated as part of going into deep
sleep. Very high risk if heaps are in RTC memory - in particular task stacks
may be in RTC memory, but also other variables.
Also fixes potential concurrency problems as RTC FAST memory is not accessible
by CPU during the CRC calculation itself.
Method:
- Disable interrupts (currently for single core only, will need update for S3)
- Load all registers before calculating CRC or going to sleep
