esp-idf

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Commit Graph

Author	SHA1	Message	Date
Omar Chebib	aa2ca7dd94	LEDC: improved support for ESP32-C3 and refactored divisor calculation As ESP32C3 does not have support for REF_TICK source clock, it is now not possible to select it anymore. Auto cfg clock has been improved for all boards.	2021-11-11 12:21:15 +08:00
SalimTerryLi	874a720286	soc/ll: workaround compiler bug that generate 8/16 bits inst instead of 32 bits one update all struct headers to be more "standardized": - bit fields are properly wrapped with struct - bitwidth sum should be 32 within same struct, so that it's correctly padded with reserved bits - bit field should be uint32_t - typedef volatile struct xxx{} yyy;: xxx must exists. refer: https://github.com/espressif/esp-idf/pull/3199 added helper macros to force peripheral registers being accessed in 32 bitwidth added a check script into ci	2021-08-30 13:50:58 +08:00
Angus Gratton	c29d93986d	soc: Add initial ESP32-C3 support From internal commit 7761d6e8	2020-11-30 11:12:56 +11:00

Author

SHA1

Message

Date

Omar Chebib

aa2ca7dd94

LEDC: improved support for ESP32-C3 and refactored divisor calculation

As ESP32C3 does not have support for REF_TICK source clock, it is now not
possible to select it anymore.
Auto cfg clock has been improved for all boards.

2021-11-11 12:21:15 +08:00

SalimTerryLi

874a720286

soc/ll: workaround compiler bug that generate 8/16 bits inst instead of 32 bits one

update all struct headers to be more "standardized":

- bit fields are properly wrapped with struct
- bitwidth sum should be 32 within same struct, so that it's correctly padded with reserved bits
- bit field should be uint32_t
- typedef volatile struct xxx{} yyy;: xxx must exists. refer: https://github.com/espressif/esp-idf/pull/3199

added helper macros to force peripheral registers being accessed in 32 bitwidth

added a check script into ci

2021-08-30 13:50:58 +08:00

Angus Gratton

c29d93986d

soc: Add initial ESP32-C3 support

From internal commit 7761d6e8

2020-11-30 11:12:56 +11:00

3 Commits