Commit Graph

20 Commits

Author SHA1 Message Date
Alexey Lapshin
40be44f827 feat(system): refactor linker scripts
- move .tbss to NOLOAD section
- remove xtensa-specific entities from riscv scripts
- explicit eh_frame terminator instead of "align magic"
- 80 characters line length limit
- refactor comments
- discard .rela sections (the rela data will go to relates sections)
2024-03-19 13:27:11 +04:00
Alexey Lapshin
824c8e0593 feat(esp_system): allow .bss to spill over into L2MEM above 0x4ff40000
This commit introduce SOC_MEM_NON_CONTIGUOUS_SRAM flag (that enebled for
esp32p4). If SOC_MEM_NON_CONTIGUOUS_SRAM is enabled:

- LDFLAGS+=--enable-non-contiguous-regions
- ldgen.py replaces "arrays[*]" from sections.ld.in with objects under
  SURROUND keyword. (e.g. from linker.lf: data -> dram0_data SURROUND(foo))
- "mapping[*]" - refers to all other data

If SOC_MEM_NON_CONTIGUOUS_SRAM, sections.ld.in file should contain at
least one block of code like this (otherwise it does not make sense):

  .dram0.bss (NOLOAD) :
  {
    arrays[dram0_bss]
    mapping[dram0_bss]
  } > sram_low

  .dram1.bss (NOLOAD) :
  {
    /* do not place here arrays[dram0_bss] because it may be splited
     * between segments */
    mapping[dram0_bss]
  } > sram_high
2024-02-28 19:41:25 +04:00
Omar Chebib
8ca191e4c1 fix(esp32p4): Fixed interrupt handling to use the CLIC controller 2023-08-31 12:16:08 +08:00
KonstantinKondrashov
cb6e2133f0 esp_hw_support: Fix invalid system time if s_esp_rtc_time_us & s_rtc_last_ticks were moved around
The commit fixes the case:
If variables in RTC RAM have been moved around by the linker,
they will be filled with garbage data. Any reset other than OTA would work fine
because the variables would still be initialized from the initial bootup.

So now system time will be valid even after OTA.

Closes https://github.com/espressif/esp-idf/issues/9448
2023-06-08 21:59:21 +08:00
KonstantinKondrashov
efbafb873b bootloader_support: Adds API to detect Factory reset has happened
Closes https://github.com/espressif/esp-idf/issues/10753
2023-03-22 02:21:54 +08:00
Marius Vikhammer
585f05596b system: fixed USE_FIXED_STATIC_RAM_SIZE option
The USE_FIXED_STATIC_RAM_SIZE was not actually causing the heap to start
at a fixed address.

Closes https://github.com/espressif/esp-idf/issues/10270
Closes https://github.com/espressif/esp-idf/issues/10271
2023-03-16 16:23:59 +08:00
Armando
0fb0be3817 ld: fixed bootloader and app potential overlap issue 2023-03-01 10:39:30 +08:00
Armando
4c878eeb0a sections_ld: add description to .flash.rodata_noload
This commit also move _rodata_reserved_end symbol right at the entry of
the .flash.rodata_noload.
2023-02-07 20:23:52 +08:00
Armando
d6844051fc esp_mm: new virtual memory mapping apis via mmu 2023-02-07 20:23:52 +08:00
wuzhenghui
44df5b31af feature: add ram loadable app support 2023-02-01 17:57:22 +08:00
jiangguangming
a367ab4b76 ld: fix rtc.data rtc.bss section issues
1. rtc.data section: should include sbss srodata in rtc_wake_stub*.*
2. rtc.bss section: move rtc .bss .bss.* from rtc.data to rtc.bss
2023-01-10 17:03:54 +08:00
Ivan Grokhotkov
523aacd413
esp_system: allow defining priorities for startup functions
* Some components have initialization dependencies. To account for
  them, simple numeric priority values are introduced.
* esp_system_init_fn_array moved into Flash from DRAM
* System init functions defined using ESP_SYSTEM_INIT_FN now return
  an error code. This enables simpler and more consistent error
  handling in the init functions. Returning an error from an init
  function is now a valid approach — the startup code will print
  an error and abort.
2022-07-12 16:58:14 +02:00
Alexey Lapshin
69b317368e esp_system: Fix esp32c2/esp32c3/esp32h2 TLS size
The change fixes thread-local-storage size by removing .srodata section
from it. It initially was included in TLS section by mistake.
The issue was found when stack size increased after building applications
with GCC-11.1 compiler. Stack size became bigger because some new data
appeared in .srodata. See more details here:
adce62f53d
2022-06-27 03:29:08 +00:00
Armando
c1cbd7bbf6 cache/mmu: implememnt cache and mmu hal APIs in bootloader 2022-03-11 22:43:11 +08:00
Eva Dengler
9fd621c7ad Fix typos.
alignement -> alignment
2022-02-25 19:32:15 +01:00
Martin Vychodil
16891e7a6c System: fix RTCFAST section alignment
This bugfix contains 3 fixes:
1. .rtc_dummy section is removed (not needed for C3)
2. .rtc_text section is padded with 16B for possible CPU prefetch
3. .rtc_text section is aligned to 4B boundary to comply with PMS Memprot requirements
2021-12-23 19:58:39 +08:00
Martin Vychodil
dd938eb952 System/Security: Memprot API unified (ESP32C3)
Unified Memory protection API for all PMS-aware chips (ESP32C3)

Closes JIRA IDF-3849
2021-12-21 01:50:36 +01:00
Mahavir Jain
e0d29d4ada esp_system: create ld template to abstract few common settings
PMS aware chips require prefetch padding size for instruction fetch, or
some memory alignment considerations. These settings are now exposed
through kconfig options (hidden) and used through common ld template.
This shall help to add and manage future chips support easily for
these considerations.

Closes IDF-3624
2021-09-02 16:13:17 +08:00
Martin Vychodil
ce28af2dd4 System/memprot: ESP32C3 IRAM section alignment fix (LD)
IRAM section didn't contain sufficient padding for possible CPU instruction prefetch,
ie instruction fetch could happen in DRAM section which is prohibited by the Memprot module.
This is fixed by adding 16B to the end of IRAM section in LD script (C3 CPU prefetch buffer depth is 4 words)

Closes IDF-3554

* fix
2021-07-23 17:11:12 +02:00
Renz Bagaporo
b06dba7823 esp32: move app linker scripts 2021-07-16 20:14:27 +08:00