Commit Graph

2039 Commits

Author SHA1 Message Date
Cao Sen Miao
1f980ae982 psram: add ESP32-D0WD-R2-V3 support 2022-02-13 22:31:24 +08:00
KonstantinKondrashov
f295efce12 esp_system: Fix RTC_WDT protection in esp_restart_noos
Fixed issue - v4.3 app not compatible with 3.1 bootloader
2022-01-10 21:57:46 +08:00
Marius Vikhammer
b1d346f682 bootloader: disable psram cache bug fix for bootloader
The psram cache bug fix was also being applied to the bootloader binary (for cmake),
which doesnt do any psram access.

Applying this fix would increase the binary size, as much as 300 bytes in worst case scenarios
2021-11-04 11:32:07 +08:00
chenjianqiang
42039cde0a add flash and PSRAM CS IO acquire function 2021-09-17 16:28:47 +08:00
Jiang Jiang Jian
3908360e46 Merge branch 'feature/support_bss_in_psram_for_esp32s2_v4.3' into 'release/v4.3'
[system] Allow .bss segment placed in external memory for ESP32-S2 ( backport v4.3)

See merge request espressif/esp-idf!14946
2021-09-15 08:09:42 +00:00
Wu Zheng Hui
4fd6d3deae Adjust the variable name &
Add mapping support for different sizes of spi ram
2021-09-15 16:09:33 +08:00
Marius Vikhammer
78392f0e84 ULP: reduce max possible memory reserved for ULP coprocessor
Some RTC slow memory is reserved by IDF, reduce CONFIG_TARGET_ULP_COPROC_RESERVE_MEM
range to reflect this.

Closes https://github.com/espressif/esp-idf/issues/7073
2021-07-31 14:10:57 +08:00
Ivan Grokhotkov
64057d302a esp32[s2,s3]: fix _flash_rodata_align value in the linker scripts
Regression from 4702feeee. The TLS segment is located inside
.flash.rodata, so we need to get the alignment of that section, not
.flash.rodata_noload.
2021-07-02 08:37:47 +02:00
Zhang Jun Hao
5e600d5b31 esp_wifi: move unused WiFi log to noload section to save binary size 2021-07-01 14:11:38 +08:00
Angus Gratton
362c9234dc Merge branch 'bugfix/fix_ld_relinking_on_modification_v4.3' into 'release/v4.3'
build: fix linker scripts edition not triggering a rebuild (backport v4.3)

See merge request espressif/esp-idf!13450
2021-06-22 00:29:11 +00:00
Angus Gratton
9f6e09d0d3 Merge branch 'bugfix/flash_rodata_any_alignement_v4.3' into 'release/v4.3'
build: Fix cache issue and add dedicated section for (Custom) App version info (backport v4.3)

See merge request espressif/esp-idf!13448
2021-06-22 00:23:49 +00:00
Angus Gratton
58a3e08895 paritition_table: Verify the partition table md5sum when loading the app
Additionally, always enable the partition MD5 check if flash encryption is on in
Release mode. This ensures the partition table ciphertext has not been modified
(CVE-2021-27926).

The exception is pre-V3.1 ESP-IDF bootloaders and partition tables, which
don't have support for the MD5 entry.
2021-05-30 23:21:14 +00:00
Omar Chebib
831d470a75 build: fix linker scripts edition not triggering a rebuild
Fix the dependencies in CMakeLists files for triggering a relink
when linker script file is modified.
2021-05-06 12:19:01 +08:00
Ivan Grokhotkov
b7707c54ce freertos: fix TLS run-time address calculation
Since dd849ffc, _rodata_start label has been moved to a different
linker output section from where the TLS templates (.tdata, .tbss)
are located. Since link-time addresses of thread-local variables are
calculated relative to the section start address, this resulted in
incorrect calculation of THREADPTR/$tp registers.

Fix by introducing new linker label, _flash_rodata_start, which points
to the .flash.rodata output section where TLS variables are located,
and use it when calculating THREADPTR/$tp.

Also remove the hardcoded rodata section alignment for Xtensa targets.
Alignment of rodata can be affected by the user application, which is
the issue dd849ffc was fixing. To accommodate any possible alignment,
save it in a linker label (_flash_rodata_align) and then use when
calculating THREADPTR. Note that this is not required on RISC-V, since
this target doesn't use TPOFF.
2021-05-06 11:42:14 +08:00
Omar Chebib
375f969d43 build: (Custom) App version info is now on a dedicated section, independent of the rodata alignment
It is now possible to have any alignment restriction on rodata in the user
applicaiton. It will not affect the first section which must be aligned
on a 16-byte bound.

Closes https://github.com/espressif/esp-idf/issues/6719
2021-05-06 11:40:57 +08:00
Omar Chebib
84dc42c4b0 gpio: Disable USB JTAG when setting pins 18 and 19 as GPIOs on ESP32C3
When `DIS_USB_JTAG` eFuse is NOT burned (`False`), it is not possible
to set pins 18 and 19 as GPIOs. This commit solves this by manually
disabling USB JTAG when using pins 18 or 19.
The functions shall use `gpio_hal_iomux_func_sel` instead of
`PIN_FUNC_SELELECT`.
2021-04-12 17:45:06 +08:00
Angus Gratton
2ed3e8b344 Merge branch 'bugfix/prefetch_invalid_v4.3' into 'release/v4.3'
soc: add dummy bytes to ensure instr prefetch always valid (v4.3)

See merge request espressif/esp-idf!12993
2021-04-09 14:49:07 +00:00
Angus Gratton
f5c6595cb4 freertos: Increase minimum task stack size when stack smashing checker is enabled
Fixes issue with DPORT init task, this task uses minimum stack size and may not be
enough if stack smashing detection is set to Overall mode.

Also reworks the way we calculate minimum stack to allow for adding multiple
contributing factors.

Closes https://github.com/espressif/esp-idf/issues/6403
2021-04-06 02:43:24 +00:00
Marius Vikhammer
5036ec363b soc: add dummy bytes to ensure instr prefetch always valid
The CPU might prefetch instructions, which means it in some cases
will try to fetch instruction located after the last instruction in
flash.text.

Add dummy bytes to ensure fetching these wont result in an error,
 e.g. MMU exceptions
2021-04-01 10:23:44 +08:00
Marius Vikhammer
c6ed522d60 deep_sleep: on S2 disable the brown out detector before deep sleeping
On S2 the brown out detector would occasionally trigger erroneously during deep sleep.

Disable it before sleeping to circumvent this issue.

Closes https://github.com/espressif/esp-idf/issues/6179
2021-02-25 10:53:06 +08:00
ninh
659d805411 esp_wifi: light sleep optimization 2021-01-18 15:31:03 +08:00
Konstantin Kondrashov
d23c7690f2 esp32c3: Add UTs for reset_reason 2021-01-18 07:12:21 +08:00
KonstantinKondrashov
dada7cd035 global: Uses CCOUNT API instead of XTHAL macro 2021-01-12 16:24:23 +08:00
Angus Gratton
db4fb49432 esp_common: Fix issue with SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY not visible on c3
Create a common symbol name to use from linker.lf fragments
2020-12-31 15:20:05 +11:00
Angus Gratton
1b0442b963 Merge branch 'feature/unify_rtc_fast_mem_as_heap_config_across_chips' into 'master'
esp_system: make rtc fast memory to heap configuration unified across chips

Closes IDF-2503

See merge request espressif/esp-idf!11693
2020-12-29 11:41:05 +08:00
xiehang
c41f4a122a esp_wifi: ESP32 phy add [sections:phy_iram] 2020-12-25 16:46:36 +08:00
Angus Gratton
c3ba995f2c Merge branch 'ci/ccomp_performance_tests' into 'master'
unit_test: Refactor all performance tests that rely on cache compensated timer

See merge request espressif/esp-idf!11709
2020-12-24 13:44:52 +08:00
Mahavir Jain
880a63b2e9 esp_system: make rtc fast memory to heap configuration unified across chips
Closes IDF-2503
2020-12-24 09:46:35 +05:30
Angus Gratton
55155c3f82 esp_system: Rename _init_start symbol to _vector_table 2020-12-24 13:40:01 +11:00
Marius Vikhammer
0a95151a75 unit_test: Refactor all performance tests that rely on cache compensated timer
There is no ccomp timer on C3, which means our performance tests will start
failing again due to variance caused by cache misses.

This MR adds TEST_PERFORMANCE_CCOMP_ macro that will only fail
performance test if CCOMP timer is supported on the target
2020-12-22 18:56:24 +11:00
Marius Vikhammer
457ce080ae AES: refactor and add HAL layer
Refactor the AES driver and add HAL, LL and caps.

Add better support for running AES-GCM fully in hardware.
2020-12-10 09:04:47 +00:00
Sachin Parekh
be5563207d esp32: Provision to redirect .bss to external ram through linker fragments
Include external ram section in the linker template to process it
through linker script generation mechanism. This enables redirection of .bss section to external memory using linker fragments

libnet80211, libpp, libbt, liblwip: Redirect .bss through fragments
2020-12-04 06:32:38 +00:00
Armando
05a4a8d864 uart: seperate sclk and baudrate setting 2020-11-24 19:12:52 +08:00
chaijie
a48b5246cc ESP32: Fix xtal 32k not oscillate or oscillate too slowly issue
ESP32 in revision0 and revision1 uses touchpad to provide
current to oscillate xtal 32k. But revision2 and revision3
do not need to do that.
Note: touchpad can not work and toupad/ULP wakeup sources
are not available when toupad provides current to xtal 32k
2020-11-23 19:38:11 +08:00
Angus Gratton
420aef1ffe Updates for riscv support
* Target components pull in xtensa component directly
* Use CPU HAL where applicable
* Remove unnecessary xtensa headers
* Compilation changes necessary to support non-xtensa gcc types (ie int32_t/uint32_t is no
  longer signed/unsigned int).

Changes come from internal branch commit a6723fc
2020-11-13 07:49:11 +11:00
Angus Gratton
66fb5a29bb Whitespace: Automated whitespace fixes (large commit)
Apply the pre-commit hook whitespace fixes to all files in the repo.

(Line endings, blank lines at end of file, trailing whitespace)
2020-11-11 07:36:35 +00:00
Angus Gratton
e82eac4354 cmake: Apply cmakelint fixes 2020-11-11 07:36:35 +00:00
KonstantinKondrashov
e9978f7623 esp32xx: Fix default values for all RTC sources in RTC_CLK_CAL_CYCLES option
Closes: https://github.com/espressif/esp-idf/issues/6037
2020-10-28 16:25:07 +08:00
Renz Bagaporo
e7460c1f00 soc: remove unecessary headers in dport_access.h 2020-10-22 19:42:34 +08:00
Renz Bagaporo
b3a7c6e27e components: remove some unneeded headers from source files 2020-10-22 19:37:10 +08:00
Angus Gratton
e5f06d7f47 Merge branch 'feature/esp32s3_support_gettimeofday' into 'master'
time: Fix gettimeofday for ESP32-S3

See merge request espressif/esp-idf!10871
2020-10-20 14:09:36 +08:00
Konstantin Kondrashov
9386cafbc3 time: Fix gettimeofday for ESP32-S3 2020-10-20 14:09:32 +08:00
Ivan Grokhotkov
48f27cb5ab Merge branch 'feature/esp32_ulp_allow_8kb' into 'master'
esp32: allow up to 8 kB of ULP program size

Closes IDFGH-1772

See merge request espressif/esp-idf!10727
2020-10-20 04:08:57 +08:00
Michael (XIAO Xufeng)
647dea9395 soc: combine xxx_caps.h into one soc_caps.h
During HAL layer refactoring and new chip bringup, we have several
caps.h for each part, to reduce the conflicts to minimum. But this is
The capabilities headers will be relataive stable once completely
written (maybe after the featues are supported by drivers).

Now ESP32 and ESP32-S2 drivers are relative stable, making it a good
time to combine all these caps.h into one soc_caps.h

This cleanup also move HAL config and pin config into separated files,
to make the responsibilities of these headers more clear. This is
helpful for the stabilities of soc_caps.h because we want to make it
public some day.
2020-10-17 16:10:15 +08:00
Marius Vikhammer
949fb8e63a SHA: add HAL layer and refactor driver
Add a LL and HAL layer for SHA.
2020-10-09 08:24:08 +00:00
Ivan Grokhotkov
ef10c2576f esp32: allow up to 8 kB of ULP program size
The remaining 4 kB had been reserved for storing RF calibration and
BT stack state since 4e092be6. However, these features never got
implemented. If we ever need to place RF related data into RTC slow
memory, we can do this by creating a variable with RTC_NOINIT_ATTR
instead.

Closes https://github.com/espressif/esp-idf/issues/3993
2020-10-05 11:41:39 +02:00
Felipe Neves
2e826b7a8f intr_alloc: split interrupt allocator into common-code and platform-code
esp_system: removed repeated interrupt allocator code and moved common code to esp_system

xtens: moved xtensa specific code from freertos to the xtensa component

hal/interrupt_controller: added interrupt controller hal and ll files

docs: update the doxyfile with new location of esp_itr_alloc.h file

xtensa: fixed dangerous relocation problem after moving xtensa interrupt files out of freertos

docs: removed Xtensa reference from intr_allocator api-reference

xtensa: pushed the interrupt function that manages non iram interrupts to the xtensa layer

esp_system/test: fixed platform dependent setting for intr_allocator tests

hal: rename the functions used to manage non iram interrupt mask.
2020-09-30 07:44:12 +08:00
Renz Bagaporo
f33f49331f ci: update configs to include/exclude esp_pm in unit test 2020-09-25 05:24:10 +00:00
Renz Bagaporo
6462f9bfe1 esp32, esp32s2: create esp_pm component 2020-09-25 05:24:10 +00:00
Wang Fang
a50966cf7a docs: update the description for RTC Clock Sources for esp32 and esp32s2 2020-09-23 17:13:19 +08:00