Marius Vikhammer
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4acfe1a91a
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ulp-riscv: always force COCPU clock on S3
The coprocessor cpu trap signal doesnt have a stable reset value,
force ULP-RISC-V clock on to stop RTC_COCPU_TRAP_TRIG_EN from waking the CPU
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2022-10-25 13:51:04 +08:00 |
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Sudeep Mohanty
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b72f987c5c
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ulp: Added ULP RISC-V support for esp32s3
This commit adds support for ULP RISC-V for esp32s3.
Signed-off-by: Sudeep Mohanty <sudeep.mohanty@espressif.com>
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2022-06-22 13:33:14 +08:00 |
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Marius Vikhammer
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386739595f
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RISCV-ULP: Add DS18B20 1wire RISCV-ULP example
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2021-06-25 11:26:39 +08:00 |
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Renz Bagaporo
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19d8a403e6
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ulp: set riscv-ulp as done signal source properly
Closes https://github.com/espressif/esp-idf/issues/6069
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2021-01-22 15:22:01 +08:00 |
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Angus Gratton
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66fb5a29bb
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Whitespace: Automated whitespace fixes (large commit)
Apply the pre-commit hook whitespace fixes to all files in the repo.
(Line endings, blank lines at end of file, trailing whitespace)
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2020-11-11 07:36:35 +00:00 |
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morris
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2917651478
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esp_rom: extract common ets apis into esp_rom_sys.h
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2020-07-27 15:27:01 +08:00 |
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Felipe Neves
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b6dba84323
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ulp: added support to building code for riscv ULP coprocessor
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2020-07-15 15:28:49 -03:00 |
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