3 Commits

Author	SHA1	Message	Date
Marius Vikhammer	c36dd7834f	core: fix cases where riscv SP were not 16 byte aligned ... RISC-V stack pointer should always be 16 byte aligned, but for some cases where we were doing manual SP manipulation this was not always the case.	2021-02-19 11:26:21 +08:00
morris	9e7d2c0065	esp32c3: format and clean up interrupt and os port code	2021-01-05 15:39:46 +08:00
Felipe Neves	ec5acf91ee	esp_shared_stack: enable shared stack function for riscv and reenable the unit test	2021-01-05 15:39:46 +08:00