Alexey Gerenkov
dfd3a9c3bc
riscv: Use semihosting to set breakpoint and watchpoint when running under debugger
2022-04-22 13:17:54 +03:00
Martin Vychodil
69096ddce5
Security: ESP32C3 memory protection feature (IRAM0/DRAM0)
...
Software support for PMS module.
Allows controlled memory access to IRAM (R/W/X) and DRAM0 (R/W)
On/locked by default, configurable in Kconfig (esp_system)
Closes https://jira.espressif.com:8443/browse/IDF-2092
2021-01-27 08:44:03 +01:00
Jakob Hasse
b51889dccb
system: stack watchpoint support on C3
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Closes IDF-2307
2021-01-14 17:46:44 +08:00
morris
7a71cedf87
interrupt: filter out reserved int number by decoding risc-v JAL instruction
2021-01-05 15:39:46 +08:00
Felipe Neves
72e4655d4e
interrupt: removed descriptor table from esp32c3 interrupt hal.
2021-01-05 15:39:46 +08:00
Felipe Neves
544a3f7df5
interrupt-allocator: reject vector allocation if its marked as not-implemented. and search to next available
2021-01-05 15:39:46 +08:00
Omar Chebib
c218f669ba
panic on RISC-V: Take into account Merge Request comments
2020-12-31 15:46:17 +08:00
Renz Bagaporo
4cc6b5571b
esp_system: support riscv panic
2020-11-13 07:49:11 +11:00
Angus Gratton
fccab8f4ef
riscv: Add new arch-level component
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Changes come from internal branch commit a6723fc
2020-11-12 09:33:18 +11:00
