4 Commits

Author	SHA1	Message	Date
Omar Chebib	5cdf145f55	refactor(riscv): refactor crosscore interrupt	2024-01-18 16:27:36 +08:00
term_est	14724d1cb9	Fix possible conversion errors by using __builtin_ffsll instead of __builtin_ffs ... Signed-off-by: term_est <62337595+term-est@users.noreply.github.com>	2023-03-03 11:21:07 +03:00
Ivan Grokhotkov	a97686f607	xtensa: fix swapped breakpoint and watchpoint numbers	2022-07-25 09:43:10 +02:00
Darian Leung	61eb7baa6b	esp_hw_support: Add esp_cpu.h abstraction and API ... This commit updates the esp_cpu.h API. The new API presents a new abstraction of the CPU where CPU presents the following interfaces: - CPU Control (to stall/unstall/reset the CPU) - CPU Registers (to read registers commonly used in SW such as SP, PC) - CPU Interrupts (to inquire/allocate/control the CPUs 32 interrupts) - Memory Port (to configure the CPU's memory bus for memory protection) - Debugging (to configure/control the CPU's debugging port) Note: Also added FORCE_INLINE_ATTR to the DoxyFile in order to pass doc builds for esp_cpu.h	2022-06-14 14:30:58 +08:00