Commit Graph

8 Commits

Author SHA1 Message Date
Omar Chebib
3c9856bdd1 (Xtensa) Build: add .xt.prop and .xt.lit to the compiled ELF file
Adding prop and lit sections to the ELF will let the debugger and the disassembler
have more info about data bytes present in the middle of the Xtensa
instructions, usually used for padding.
2022-07-05 04:39:29 +00:00
Alexey Lapshin
69b317368e esp_system: Fix esp32c2/esp32c3/esp32h2 TLS size
The change fixes thread-local-storage size by removing .srodata section
from it. It initially was included in TLS section by mistake.
The issue was found when stack size increased after building applications
with GCC-11.1 compiler. Stack size became bigger because some new data
appeared in .srodata. See more details here:
adce62f53d
2022-06-27 03:29:08 +00:00
Armando
b5de3ec953 esp_common: rename EXT_RAM_ATTR to EXT_RAM_BSS_ATTR to make it clearer
EXT_RAM_ATTR is deprecated. To put .bss on PSRAM, use this new macro EXT_RAM_BSS_ATTR
2022-04-19 19:48:00 +08:00
Armando
f8249550f8 psram: support .bss on psram on esp32s3 2022-04-19 19:48:00 +08:00
Omar Chebib
b0afae5e60 espcoredump: fix a bug where tracked DRAM data where not dumped
Variables marked as COREDUMP_DRAM_ATTR will now be part of the core dump.

* Closes https://github.com/espressif/esp-idf/issues/8151
2022-01-06 16:53:35 +08:00
Mahavir Jain
e0d29d4ada esp_system: create ld template to abstract few common settings
PMS aware chips require prefetch padding size for instruction fetch, or
some memory alignment considerations. These settings are now exposed
through kconfig options (hidden) and used through common ld template.
This shall help to add and manage future chips support easily for
these considerations.

Closes IDF-3624
2021-09-02 16:13:17 +08:00
Wu Zheng Hui
3128a2544b Adjust the variable name &
Add mapping support for different sizes of spi ram
2021-08-25 16:06:28 +08:00
Renz Bagaporo
b06dba7823 esp32: move app linker scripts 2021-07-16 20:14:27 +08:00