Commit Graph

69 Commits

Author SHA1 Message Date
Angus Gratton
d4c9a45675 spi_flash: Add ESP32-C3 support
Based on internal commit 3ef01301fff
2020-12-17 15:34:13 +11:00
Angus Gratton
5228d9f9ce esp32c3: Apply one-liner/small changes for ESP32-C3 2020-12-01 10:58:50 +11:00
Cao Sen Miao
11188d2143 esp_flash:fix bug about clearing WLE automatically after actions 2020-11-12 16:44:29 +08:00
Renz Bagaporo
21e46d5b3c ci: use actual esp_system headers for host test 2020-10-22 19:42:34 +08:00
Renz Bagaporo
b3a7c6e27e components: remove some unneeded headers from source files 2020-10-22 19:37:10 +08:00
morris
61f89b97c6 bringup esp32-s3 on FPGA 2020-09-22 15:15:03 +08:00
Michael (XIAO Xufeng)
fefdee1349 bootloader: fix the WRSR format for ISSI flash chips
1. The 2nd bootloader always call `rom_spiflash_unlock()`, but never help to clear the WEL bit when exit. This may cause system unstability.

   This commit helps to clear WEL when flash configuration is done.

   **RISK:** When the app starts, it didn't have to clear the WEL before it actually write/erase. But now the very first write/erase operation should be done after a WEL clear. Though the risk is little (all the following write/erase also need to clear the WEL), we still have to test this carefully, especially for those functions used by the OTA.

2. The `rom_spiflash_unlock()` function in the patch of ESP32 may (1) trigger the QPI, (2) clear the QE or (3) fail to unlock the ISSI chips.

   Status register bitmap of ISSI chip and GD chip:

| SR | ISSI | GD25LQ32C |
| -- | ---- | --------- |
| 0  | WIP  | WIP       |
| 1  | WEL  | WEL       |
| 2  | BP0  | BP0       |
| 3  | BP1  | BP1       |
| 4  | BP2  | BP2       |
| 5  | BP3  | BP3       |
| 6  | QE   | BP4       |
| 7  | SRWD | SRP0      |
| 8  |      | SRP1      |
| 9  |      | QE        |
| 10 |      | SUS2      |
| 11 |      | LB1       |
| 12 |      | LB2       |
| 13 |      | LB3       |
| 14 |      | CMP       |
| 15 |      | SUS1      |

   QE bit of other chips are at the bit 9 of the status register (i.e. bit 1 of SR2), which should be read by RDSR2 command.

   However, the RDSR2 (35H, Read Status 2) command for chip of other vendors happens to be the QIOEN (Enter QPI mode) command of ISSI chips. When the `rom_spiflash_unlock()` function trys to read SR2, it may trigger the QPI of ISSI chips.

   Moreover, when `rom_spiflash_unlock()` try to clear the BP4 bit in the status register, QE (bit 6) of ISSI chip may be cleared by accident. Or if the ISSI chip doesn't accept WRSR command with argument of two bytes (since it only have status register of one byte), it may fail to clear the other protect bits (BP0~BP3) as expected.

   This commit makes the `rom_spiflash_unlock()` check whether the vendor is issi. if so, `rom_spiflash_unlock()` only send RDSR to read the status register, send WRSR with only 1 byte argument, and also avoid clearing the QE bit (bit 6).

3. `rom_spiflash_unlock()` always send WRSR command to clear protection bits even when there is no protection bit active. And the execution of clearing status registers, which takes about 700us, will also happen even when there's no bits cleared.

   This commit skips the clearing of status register if there is no protection bits active.

Also move the execute_flash_command to be a bootloader API; move
implementation of spi_flash_wrap_set to the bootloader
2020-09-19 10:51:51 +08:00
Michael (XIAO Xufeng)
479269a52b Merge branch 'feature/configure_flash_write_chunk_size' into 'master'
spi_flash: add configuration option to select flash write chunk size

See merge request espressif/esp-idf!9067
2020-06-22 14:50:42 +08:00
Mahavir Jain
05da91f0db spi_flash: add configuration option to select flash write chunk size
Flash write operation is broken down into smaller chunk writes. Size
of this chunk was previously set to 8K but that in-turn meant cache and
non-IRAM resident interrupts could stay disabled upto ~24msec for 8K flash
write operation. If chunk size is brought down to 256 (typical flash page size)
then it brings down cache and non-IRAM interrupts disable duration to ~1msec.

Fix here keeps defaults same but provides configuration option to tweak the
setting based on application requirement.
2020-06-05 14:45:41 +05:30
Ivan Grokhotkov
03bb2774d9 spi_flash: don't call vTaskDelay in non-os context
Fixes regression in core dump, when a crash happens in interrupt
context.
2020-06-02 15:42:24 +02:00
Darian Leung
11d96b39d0 esp_ipc: Move to new component
This commit moves esp_ipc into a separate component.
2020-05-18 16:51:45 +08:00
KonstantinKondrashov
304f67e42a spi_flash(LEGACY_IMPL): Add a Kconfig option - Bypass a block erase and always do sector erase
Closes: IDF-1561
2020-04-30 13:58:13 +08:00
KonstantinKondrashov
3cb655eaab spi_flash(LEGACY_IMPL): Add vTaskDelay while a long erasing
Added Kconfig options to enable yield operation during flash erase

Closes: https://github.com/espressif/esp-idf/issues/2083
Closes: https://github.com/espressif/esp-idf/issues/4916
Closes: IDFGH-261
2020-04-30 13:58:13 +08:00
Angus Gratton
dbdce93d23 spi_flash: Use per-chip flash_ops files for legacy API
Looks like when ESP32-S2 Beta support was merged, the separate files
were dropped by accident.
2020-04-24 12:43:47 -03:00
morris
e30cd361a8 global: rename esp32s2beta to esp32s2 2020-01-22 12:14:38 +08:00
morris
1c2cc5430e global: bring up esp32s2(not beta) 2020-01-16 17:41:31 +08:00
Michael (XIAO Xufeng)
2660cb82ae spi_flash: support to verify written encrypted data
Also add unit test for encrypted_read
2019-10-30 05:49:50 +00:00
Angus Gratton
8675a818f9 Merge branch 'master' into feature/esp32s2beta_merge 2019-10-22 13:51:49 +11:00
Ajita Chavan
56f73d7720 flash_ops: fix spi_flash_read with source buffer not from internal memory and size < 16
Closes https://github.com/espressif/esp-idf/issues/4010
2019-10-19 14:56:43 +08:00
Angus Gratton
438d513a95 Merge branch 'master' into feature/esp32s2beta_merge 2019-09-16 16:18:48 +10:00
wanglei
653d8b5bdd update cache and spiram related files and bug fixes
1. remove speed dependency of SPIRAM
2. support wrap mode of cache, flash and SPIRAM
3. fix some bugs on cache modes support
2019-09-05 14:14:49 +08:00
Ivan Grokhotkov
12c9d9a564 spi_flash: remove duplicate definition of spi_flash_unlock
The other (static) definition is in flash_ops.c, all references are
also in flash_ops.c.
2019-08-23 12:37:55 +08:00
Angus Gratton
309376f51a spi_flash: Force legacy mode for ESP32-S2
Can be removed once IDF-763 is merged
2019-08-13 17:14:16 +10:00
Angus Gratton
04ae56806c Merge branch 'master' into feature/esp32s2beta_update 2019-08-08 15:26:58 +10:00
Angus Gratton
24d26fccde Merge branch 'master' into feature/esp32s2beta_update 2019-08-08 13:44:24 +10:00
Anton Maklakov
afbaf74007 tools: Mass fixing of empty prototypes (for -Wstrict-prototypes) 2019-08-01 16:28:56 +07:00
Ivan Grokhotkov
1c17558e6e spi_flash: use same argument types in .h and .c files
Fixes compilations on targets where size_t != uint32_t
2019-07-02 10:26:06 +02:00
Michael (XIAO Xufeng)
1036a091fe spi_flash: support working on differnt buses and frequency 2019-06-18 06:32:52 +00:00
Roland Dobai
22d070e0af spi_flash: Rename long Kconfig options 2019-06-12 08:03:07 +02:00
suda-morris
84b2f9f14d build and link hello-world for esp32s2beta 2019-06-11 13:07:37 +08:00
Michael (XIAO Xufeng)
562af8f65e global: move the soc component out of the common list
This MR removes the common dependency from every IDF components to the SOC component.

Currently, in the ``idf_functions.cmake`` script, we include the header path of SOC component by default for all components.
But for better code organization (or maybe also benifits to the compiling speed), we may remove the dependency to SOC components for most components except the driver and kernel related components.

In CMAKE, we have two kinds of header visibilities (set by include path visibility):

(Assume component A --(depends on)--> B, B is the current component)

1. public (``COMPONENT_ADD_INCLUDEDIRS``): means this path is visible to other depending components (A) (visible to A and B)
2. private (``COMPONENT_PRIV_INCLUDEDIRS``): means this path is only visible to source files inside the component (visible to B only)

and we have two kinds of depending ways:

(Assume component A --(depends on)--> B --(depends on)--> C, B is the current component)

1. public (```COMPONENT_REQUIRES```): means B can access to public include path of C. All other components rely on you (A) will also be available for the public headers. (visible to A, B)
2. private (``COMPONENT_PRIV_REQUIRES``): means B can access to public include path of C, but don't propagate this relation to other components (A). (visible to B)

1. remove the common requirement in ``idf_functions.cmake``, this makes the SOC components invisible to all other components by default.
2. if a component (for example, DRIVER) really needs the dependency to SOC, add a private dependency to SOC for it.
3. some other components that don't really depends on the SOC may still meet some errors saying "can't find header soc/...", this is because it's depended component (DRIVER) incorrectly include the header of SOC in its public headers. Moving all this kind of #include into source files, or private headers
4. Fix the include requirements for some file which miss sufficient #include directives. (Previously they include some headers by the long long long header include link)

This is a breaking change. Previous code may depends on the long include chain.
You may need to include the following headers for some files after this commit:

- soc/soc.h
- soc/soc_memory_layout.h
- driver/gpio.h
- esp_sleep.h

The major broken include chain includes:

1. esp_system.h no longer includes esp_sleep.h. The latter includes driver/gpio.h and driver/touch_pad.h.
2. ets_sys.h no longer includes soc/soc.h
3. freertos/portmacro.h no longer includes soc/soc_memory_layout.h

some peripheral headers no longer includes their hw related headers, e.g. rom/gpio.h no longer includes soc/gpio_pins.h and soc/gpio_reg.h

BREAKING CHANGE
2019-04-16 13:21:15 +08:00
morris
c159984264 separate rom from esp32 component to esp_rom
1. separate rom include files and linkscript to esp_rom
2. modefiy "include rom/xxx.h" to "include esp32/rom/xxx.h"
3. Forward compatible
4. update mqtt
2019-03-21 18:51:45 +08:00
morris
956c25dedd move esp32 chip specific includes to esp32/xxx.h 2019-03-18 17:14:05 +08:00
Mahavir Jain
2752654043 spi_flash: fix stale read issue for memory mapped partition
On flash program operation (either erase or write), if corresponding address has
cache mapping present then cache is explicitly flushed (for both pro and app cpu)

Closes https://github.com/espressif/esp-idf/issues/2146
2019-03-13 05:38:01 +00:00
Alexey Gerenkov
78a7a152d1 esp32: Fixes freezing core dump process when flash write address checks are enabled 2018-11-15 06:13:48 +00:00
Mahavir Jain
8227db4f5e spi_flash: fix erase_range for block erase check
Erase in block (64k) as much as possible, before falling back
to sector (4k) erase.

Signed-off-by: Mahavir Jain <mahavir@espressif.com>
2018-08-29 12:04:32 +00:00
Angus Gratton
f7ac41c2da spi_flash: Add option to log warnings if (spuriously) writing zero bits to ones
Won't work for SPIFFS, maybe some other implementations?
2017-12-04 09:55:05 +11:00
Angus Gratton
892b3ff14b spi_flash: Add option to verify all writes by reading back data
Helpful when debugging SPI flash hardware related issues.

TW15203
2017-12-04 09:55:05 +11:00
Angus Gratton
7a924bd85a spi_flash: Expose an accessor the current SPI flash guard functions
Change places which uses g_flash_guard_default_ops to use this. Probably exact same data, but a bit
cleaner.
2017-11-20 15:54:31 +11:00
Angus Gratton
670733df9f spi_flash: Abort on writes to dangerous regions (bootloader, partition table, app)
Can be disabled or made into a failure result in kconfig if needed.
2017-11-03 15:52:27 -07:00
Ivan Grokhotkov
fbd52dcf34 spi_flash: fix build error with profiling enabled 2017-10-22 12:57:56 +08:00
Ivan Grokhotkov
59b7d98fec Merge branch 'feature/dfs' into 'master'
Dynamic frequency scaling

See merge request !1189
2017-10-22 12:34:11 +08:00
Ivan Grokhotkov
8990549e89 spi_flash: fix spi_flash_read into buffer in external RAM, add test 2017-10-19 21:35:21 +08:00
Ivan Grokhotkov
bfeecd2b56 freertos: deprecate XT_CLOCK_FREQ
- freertos: add deprecated definition for XT_CLOCK_FREQ
- flash_ops: don't use XT_CLOCK_FREQ
- unity: don't use XT_CLOCK_FREQ
- hw_random: don't use XT_CLOCK_FREQ
- core_dump: don't use XT_CLOCK_FREQ
- app_trace: don't use XT_CLOCK_FREQ
- xtensa_init: init xt_tick_divisor
2017-10-18 14:19:19 +08:00
Angus Gratton
11d2db40f4 spi_flash: Fix SPI flash write alignment/size bugs
* Writing >4 bytes to unaligned offsets would fail
* Writiing data from flash would fail (wrong buffer was used)
* Writing >8192 bytes from RAM would over-write data multiple times

Adds test cases for the above.
2017-06-09 17:33:27 +10:00
Alexey Gerenkov
0860f46220 spi_flash: Fixed bug in SPI flash ROM driver to work with embedded flash chip
1) fixed SPI_read_status: added check for flash busy flag in matrix mode
2) fixed SPI_page_program: enable write before writing data to SPI FIFO
3) SPI flash ROM funcs replacement is controlled via menuconfig option
2017-04-11 10:51:19 +08:00
Angus Gratton
8352e7e9ec unit test: Measure test wall time with CCOUNT, so it includes time w/ interrupts off 2017-03-22 15:35:54 +08:00
Angus Gratton
d8fda48551 spi_flash: Split large SPI flash operations into parts, allowing preemption
* Erase range operations allow preemption after each block or sector.
* Write operations allow preemption every 8KB of data.
* Reado operations allow preemption every 16KB of data.
2017-03-22 15:35:54 +08:00
Ivan Grokhotkov
cbb71baca9 spi_flash: protect spi_flash_unlock
spi_flash_unlock was missing spi_flash_guard_start, which caused cache
to be enabled during unlock operation, causing hard-to-trace crashes
and cache data corruption.
2017-02-22 12:51:16 +08:00
Alexey Gerenkov
04acc88023 esp32: Fixes watchdog problem when printing core dump to uart
Also fixes generation of core dumps when flash cache is disabled
2017-02-01 18:39:28 +03:00