Marius Vikhammer
77ba84eeb7
ulp-fsm: Update ulp-fsm ADC example with S3 support
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Closes https://github.com/espressif/esp-idf/issues/7963
2022-09-07 16:48:06 +08:00
Sudeep Mohanty
4fde033a5f
ulp: Added support for RTC I2C driver for ULP RISC-V on esp32s2 and esp32s3
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This commit adds support for using the RTC I2C peripheral on the ULP
RISC-V core for esp32s2 and esp32s3. It also adds an example to demonstrate the
usage of the RTC I2C peripheral.
This commit also modifies the rtc_i2c register structure files to enable
the use of bitfields in the ULP RISC-V RTC I2C driver.
2022-09-05 10:21:43 +02:00
Marius Vikhammer
ffed60cc93
ulp-riscv: added lock API to provide mutual exclusion when sharing variables between the main CPU and the ULP.
2022-08-05 18:16:31 +08:00
Marius Vikhammer
af329784b1
ulp: fix missing cpp header guard
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https://github.com/espressif/esp-idf/issues/9464
2022-08-01 10:19:32 +08:00
Armando
5b523a3313
esp_adc: new esp_adc component and adc drivers
2022-07-15 18:31:00 +08:00
Marius Vikhammer
e8b5096f52
ulp-riscv: add support for using ADC as well as an example show-casing it.
2022-07-11 09:31:22 +08:00
Marius Vikhammer
c8617fe965
docs: fix all doxygen warnings
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Doxygen warnings would previously not result in a failed pipeline.
Fixed this as well as all current warnings.
2022-05-12 14:50:03 +08:00
Marius Vikhammer
c974a000d7
ULP: Add example of using GPIO to wakeup the ULP-RISCV processor
2022-02-28 14:15:25 +08:00
Marius Vikhammer
8a48b55197
ulp: change deprecated headers to use relative includes to avoid recursivly including the same header
2022-02-11 14:56:11 +08:00
Sudeep Mohanty
2fc9bd61bf
ulp: refactor ulp component
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This commit refactors the ulp component.
Files are now divided based on type of ulp, viz., fsm or risc-v.
Files common to both are maintained in the ulp_common folder.
This commit also adds menuconfig options for ULP within the ulp
component instead of presenting target specific configuations for ulp.
2022-01-27 11:54:42 +05:30
Marius Vikhammer
ff6f927b5f
ULP: add functions for stopping/restarting the ulp-riscv
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Closes https://github.com/espressif/esp-idf/issues/8232
2022-01-20 11:34:53 +08:00
Sudeep Mohanty
2ed15d8b1e
ulp: Added ULP RISC-V support for esp32s3
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This commit adds support for ULP RISC-V for esp32s3.
Signed-off-by: Sudeep Mohanty <sudeep.mohanty@espressif.com>
2022-01-18 10:58:00 +05:30
Marius Vikhammer
386739595f
RISCV-ULP: Add DS18B20 1wire RISCV-ULP example
2021-06-25 11:26:39 +08:00
Angus Gratton
66fb5a29bb
Whitespace: Automated whitespace fixes (large commit)
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Apply the pre-commit hook whitespace fixes to all files in the repo.
(Line endings, blank lines at end of file, trailing whitespace)
2020-11-11 07:36:35 +00:00
Felipe Neves
b6dba84323
ulp: added support to building code for riscv ULP coprocessor
2020-07-15 15:28:49 -03:00
