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76 Commits

Author SHA1 Message Date
Angus Gratton
61b70c50a4 freertos: Use the standard assert() function for configASSERT 
Unless the option for "assert and keep running" is enabled.

This means that silent asserts now work for FreeRTOS, and disabling asserts
now also disables them in FreeRTOS without needing a separate config change.

Related to https://github.com/espressif/esp-idf/issues/6306
 2021-03-03 10:26:57 +11:00
Angus Gratton
d6f4d99d93 core system: Fix warnings in compilation when assertions are disabled 
Adds a CI config for hello world that sets this, to catch future regressions
 2021-03-03 10:26:57 +11:00
Renz Bagaporo
0f03f450ff esp_hw_support: create esp_cpu 
Create a esp_cpu header that contains CPU-related functions and
utilities.
 2021-02-26 13:34:29 +08:00
Omar Chebib
78a94dbb6c freertos: Fix delay between interrupt request and trigger on RISC-V 
NOP instructions have been added in order to prevent the code
from executing code it shouldn't execute. This is due to a delay
between the moment an interrupt is requested and the moment it
is fired. It only happens on RISC-V SoC.
 2021-02-25 06:57:59 +00:00
Marius Vikhammer
311a0fa5e8 freertos: add API for getting tick rate on C3 2021-02-23 12:05:52 +08:00
Marius Vikhammer
c36dd7834f core: fix cases where riscv SP were not 16 byte aligned 
RISC-V stack pointer should always be 16 byte aligned, but for some cases where
we were doing manual SP manipulation this was not always the case.
 2021-02-19 11:26:21 +08:00
Marius Vikhammer
eec2419390 system: enable shared stack watchpoint 
Enable shared stack watchpoint for overflow detection

Enable unit tests:
 * "test printf using shared buffer stack" for C3
 * "Test vTaskDelayUntil" for S2
 * "UART can do poll()" for C3
 2021-02-18 15:38:30 +08:00
Marius Vikhammer
04df1f3a42 CI: enable example builds for C3 
Enables building C3 examples in CI.

Fixes related warnings/errors and disables examples that cannot run.
 2021-02-09 12:04:02 +08:00
Angus Gratton
bc09dda0f4 docs: Update SMP descriptions for taskENTER_CRITICAL/taskEXIT_CRITICAL 
Closes https://github.com/espressif/esp-idf/issues/6259
 2021-02-05 10:18:23 +11:00
Ivan Grokhotkov
bb1f75179b Merge branch 'bugfix/freertos_systimer_stall_when_cpu_halted' into 'master' 
freertos: stall systimer while CPU is in debug mode

See merge request espressif/esp-idf!12063
 2021-01-29 07:02:30 +08:00
Angus Gratton
cc934ea0a1 Merge branch 'feature/esp32c3_tls' into 'master' 
freertos: add thread local storage support in RISC-V port

Closes IDF-2125

See merge request espressif/esp-idf!12064
 2021-01-27 15:19:06 +08:00
Marius Vikhammer
4374966d4e freerots: fix rtos_int_exit writing outside ISR stack 
rtos_int_exit would store RA at an offset of 4 byte from the SP,
where the offset should be 0.

This caused rtos_int_exit to overwrite variables in bss.
 2021-01-26 11:18:39 +00:00
Ivan Grokhotkov
b2aaebaf85 freertos: add thread local storage support in RISC-V port 2021-01-24 12:38:15 +00:00
Ivan Grokhotkov
d7bac619ec freertos: stall systimer while CPU is in debug mode 2021-01-24 11:32:17 +00:00
Li Shuai
63c4e5481f fix no RTOS SysTick interrupt for a period of time after the OS Scheduler is started 2021-01-19 14:51:22 +08:00
Li Shuai
355dd10257 light sleep: dfs support for esp32c3 2021-01-19 14:50:58 +08:00
Jakob Hasse
b51889dccb system: stack watchpoint support on C3 
Closes IDF-2307
 2021-01-14 17:46:44 +08:00
morris
753a929525 global: fix sign-compare warnings 2021-01-12 14:05:08 +08:00
morris
9e7d2c0065 esp32c3: format and clean up interrupt and os port code 2021-01-05 15:39:46 +08:00
Felipe Neves
544a3f7df5 interrupt-allocator: reject vector allocation if its marked as not-implemented. and search to next available 2021-01-05 15:39:46 +08:00
Felipe Neves
ec5acf91ee esp_shared_stack: enable shared stack function for riscv and reenable the unit test 2021-01-05 15:39:46 +08:00
Felipe Neves
f4781d3b1d freertos: riscv port now uses interrupt allocator and crosscore interrupt 2021-01-05 15:39:46 +08:00
Felipe Neves
810be86f21 freertos/riscv: move freertos aware interrupt code from vectors to the freertos riscv port. 
The riscv vectors.S in riscv component contains the trap vector, which is responsible to
defer interrupts and examine if a task context switch is needed, this change cleans up
this code by hiding all freertos details behind on two functions rtos_it_enter/exit and
their implementations are placed in freertos riscv port files.
 2021-01-05 15:39:46 +08:00
Ivan Grokhotkov
7f3b16a99d freertos: always enable static allocation 
to use it for newlib locks
 2020-12-29 16:18:04 +01:00
Angus Gratton
5228d9f9ce esp32c3: Apply one-liner/small changes for ESP32-C3 2020-12-01 10:58:50 +11:00
Angus Gratton
87e13baaf1 freertos: Add RISC-V port 
Changes come from internal branch commit a6723fc
 2020-11-13 07:49:11 +11:00