Some additional checks related to secure version of the application in
anti-rollback case have been added to avoid any attempts to boot lower
security version but valid application (e.g., passive partition image).
- Read secure_version under sha256 protection
- First check has been added in the bootloader to ensure correct secure
version after application verification and loading stage. This check
happens before setting up the flash cache mapping and handling over
the final control to application. This check ensures that application
was not swapped (e.g., to lower security version but valid image) just
before the load stage in bootloader.
- Second check has been added in the application startup code to ensure
that currently booting app has higher security version than the one
programmed in the eFuse for anti-rollback scenario. This will ensure
that only the legit application boots-up on the device for
anti-rollback case.
When the macro was introduced, a semicolon was added at the end
of the definition and merged like that in v5.2 release. The semicolon
was then removed in master but the change was never backported in v5.2.
This commit removes the semicolon to the definition of the PATCKED_ATTR
macro in v5.2.
Closes https://github.com/espressif/esp-idf/issues/13149
* Closes https://github.com/espressif/esp-idf/issues/12849
In former versions of ESP-IDF, the user custom memory data in the retained memory
was taken into account during the CRC calculation. This was changed in a later
commit, the custom memory was ignored, therefore this can seen as a breaking change.
This commit gives the possibility to choose between the former (legacy) or
new way of calculating the CRC.
There are a bunch of cases you might want some pins not exposed.
Eg.
* Reading say 8 bit data and outputting the top 5 bits, discarding the rest by not mapping those data pins to output pins
* Not using hsync/vsync because sync data is embedded within the data bits for more timing flexibility (eg. interlacing).
* Using the LCD module as a high speed parallel data output bus, with no need for sync/control pins.
Removing this validation makes these cases work.
Merges https://github.com/espressif/esp-idf/pull/13103
1. Fixed BLE 2M phy TX problem causing by phy_wifi_enable_set() on ESP32-C3 and ESP32-S3
2. Fixed BLE CCA bug on ESP32-C2
3. Fixed wifi boot bug at low temp on ESP32-C6
4. Fixed BLE and WIFI could not receive packets after entering light sleep for a long time on ESP32-C3, ESP32-S3, ESP32-C2 and ESP32-C6
For C6/H2/P4/C5, there is no SoC specific debug range. Instead the same
address range is part of CPU Subsystem range which contains debug mode
specific code and interrupt config registers (CLINT, PLIC etc.).
For now the PMP entry is provided with RWX permission for both machine
and user mode but we can save this entry and allow the access to only
machine mode for this range.
For P4/C5 case, this PMP entry can have RW permission as the debug mode
specific code is not present in this memory range.
