Commit Graph

52 Commits

Author SHA1 Message Date
Michael (XIAO Xufeng)
31955fd7ea i2c: modify internal impl to ensure the cmd will not be modified
related to: https://github.com/espressif/esp-idf/issues/5108
2021-01-27 01:31:49 +08:00
Sachin Parekh
6e1f53bce3 i2c: Acquire PM lock after acquiring mutex 2020-12-22 00:50:19 +05:30
Angus Gratton
5228d9f9ce esp32c3: Apply one-liner/small changes for ESP32-C3 2020-12-01 10:58:50 +11:00
Cao Sen Miao
31afe8109f i2c: Fix bug on i2c clk allocator 2020-11-25 14:26:37 +08:00
Cao Sen Miao
6eee601cf6 i2c: Add supports on esp32s3 2020-11-12 11:32:45 +08:00
Michael (XIAO Xufeng)
647dea9395 soc: combine xxx_caps.h into one soc_caps.h
During HAL layer refactoring and new chip bringup, we have several
caps.h for each part, to reduce the conflicts to minimum. But this is
The capabilities headers will be relataive stable once completely
written (maybe after the featues are supported by drivers).

Now ESP32 and ESP32-S2 drivers are relative stable, making it a good
time to combine all these caps.h into one soc_caps.h

This cleanup also move HAL config and pin config into separated files,
to make the responsibilities of these headers more clear. This is
helpful for the stabilities of soc_caps.h because we want to make it
public some day.
2020-10-17 16:10:15 +08:00
Chen Yi Qun
caaf62bdad driver, http_client, web_socket, tcp_transport: remove __FILE__ from log messages
__FILE__ macro in the error messages adds full paths to the production binarys, remove __FILE__ from the ESP_LOGE.

Closes https://github.com/espressif/esp-idf/issues/5637
Merges https://github.com/espressif/esp-idf/pull/5638
2020-08-03 15:21:36 +08:00
Ivan Grokhotkov
16c73edc67 Merge branch 'refactor/add_alias_name_for_ets_common_api' into 'master'
esp_rom: extract common ets apis into esp_rom_sys.h

See merge request espressif/esp-idf!9701
2020-07-28 15:04:55 +08:00
Michael (XIAO Xufeng)
1aabab0160 Merge branch 'bugfix/i2c_const_function_signature' into 'master'
I2C: add const to signature of master_write function

Closes IDFGH-3324

See merge request espressif/esp-idf!9306
2020-07-27 16:31:20 +08:00
morris
2917651478 esp_rom: extract common ets apis into esp_rom_sys.h 2020-07-27 15:27:01 +08:00
morris
a4d0033c03 esp_rom: extract common GPIO apis into esp_rom_gpio.h 2020-07-07 11:40:19 +08:00
Peter Schaefer
f08743e452 Added const for pointer in master_write method, so that a const array can be passed to this fcn.
Signed-off-by: wubowen <wubowen@espressif.com>

Merges https://github.com/espressif/esp-idf/pull/5307

explicitly convert a const ptr to non-const because we actually don't modify it.
2020-07-06 03:37:39 +00:00
Michael (XIAO Xufeng)
661f4c430d Merge branch 'feature/esp32s2_i2c_driver' into 'master'
Feature:  Add esp32-s2 I2C driver.

Closes IDF-1278 and IDF-1026

See merge request espressif/esp-idf!7680
2020-03-26 10:20:40 +08:00
Jakob Hasse
3bcc6b48af I2C: i2c.h/i2c.c applied new code formatting 2020-02-26 15:12:03 +08:00
houwenxiang
4883733472 driver(I2C): support esp32-s2 I2C driver. 2020-02-25 21:56:00 +08:00
Jakob Hasse
d230d44e2d I2C: const correctness, checking SDA/SCL GPIOs
* const correctness in i2c_slave_write_buffer()
* i2c_set_pin() additionally checks whether
  SDA and SCL pins are the same number
2020-02-24 14:30:28 +08:00
houwenxiang
aac935ec81 bugfix(i2c): fix I2C driver breaking change issue.
1. Fixed I2C driver breaking change issue.
    2. Add I2C UT test case.
2019-12-04 15:51:36 +08:00
houwenxiang
28286183d1 feature(I2C): Add i2c hal support. 2019-11-21 20:34:07 +08:00
Angus Gratton
04ae56806c Merge branch 'master' into feature/esp32s2beta_update 2019-08-08 15:26:58 +10:00
Anton Maklakov
afbaf74007 tools: Mass fixing of empty prototypes (for -Wstrict-prototypes) 2019-08-01 16:28:56 +07:00
chenjianqiang
667113cf94 feat(i2c): update i2c driver for esp32s2beta 2019-07-10 11:41:36 +08:00
Angus Gratton
2331597ed2 Merge branch 'bugfix/ticks_to_wait_for_uart_and_i2c' into 'master'
driver: Fix ticks_to_wait for uart and i2c

Closes IDFGH-964

See merge request idf/esp-idf!5021
2019-06-11 08:41:44 +08:00
Konstantin Kondrashov
22a30e2740 i2c: Fix ticks_to_wait when 0 or time expired
Closes: https://github.com/espressif/esp-idf/issues/3301

Closes: IDFGH-964
2019-06-04 11:50:54 +08:00
Konstantin Kondrashov
399d2d2605 all: Using xxx_periph.h
Using xxx_periph.h in whole IDF instead of xxx_reg.h, xxx_struct.h, xxx_channel.h ... .

Cleaned up header files from unnecessary headers (releated to soc/... headers).
2019-06-03 14:15:08 +08:00
Michael (XIAO Xufeng)
562af8f65e global: move the soc component out of the common list
This MR removes the common dependency from every IDF components to the SOC component.

Currently, in the ``idf_functions.cmake`` script, we include the header path of SOC component by default for all components.
But for better code organization (or maybe also benifits to the compiling speed), we may remove the dependency to SOC components for most components except the driver and kernel related components.

In CMAKE, we have two kinds of header visibilities (set by include path visibility):

(Assume component A --(depends on)--> B, B is the current component)

1. public (``COMPONENT_ADD_INCLUDEDIRS``): means this path is visible to other depending components (A) (visible to A and B)
2. private (``COMPONENT_PRIV_INCLUDEDIRS``): means this path is only visible to source files inside the component (visible to B only)

and we have two kinds of depending ways:

(Assume component A --(depends on)--> B --(depends on)--> C, B is the current component)

1. public (```COMPONENT_REQUIRES```): means B can access to public include path of C. All other components rely on you (A) will also be available for the public headers. (visible to A, B)
2. private (``COMPONENT_PRIV_REQUIRES``): means B can access to public include path of C, but don't propagate this relation to other components (A). (visible to B)

1. remove the common requirement in ``idf_functions.cmake``, this makes the SOC components invisible to all other components by default.
2. if a component (for example, DRIVER) really needs the dependency to SOC, add a private dependency to SOC for it.
3. some other components that don't really depends on the SOC may still meet some errors saying "can't find header soc/...", this is because it's depended component (DRIVER) incorrectly include the header of SOC in its public headers. Moving all this kind of #include into source files, or private headers
4. Fix the include requirements for some file which miss sufficient #include directives. (Previously they include some headers by the long long long header include link)

This is a breaking change. Previous code may depends on the long include chain.
You may need to include the following headers for some files after this commit:

- soc/soc.h
- soc/soc_memory_layout.h
- driver/gpio.h
- esp_sleep.h

The major broken include chain includes:

1. esp_system.h no longer includes esp_sleep.h. The latter includes driver/gpio.h and driver/touch_pad.h.
2. ets_sys.h no longer includes soc/soc.h
3. freertos/portmacro.h no longer includes soc/soc_memory_layout.h

some peripheral headers no longer includes their hw related headers, e.g. rom/gpio.h no longer includes soc/gpio_pins.h and soc/gpio_reg.h

BREAKING CHANGE
2019-04-16 13:21:15 +08:00
morris
f5b03c9ea3 misc adjustment of esp32 component 2019-04-03 19:57:46 +08:00
Ivan Grokhotkov
060cf9d6b4 Merge branch 'power_management/i2s+i2c' into 'master'
Power management/i2s+i2c

See merge request idf/esp-idf!4338
2019-03-19 17:27:59 +08:00
Ivan Grokhotkov
f0a82d7185 driver/i2c: write i2c command structure to hardware in one operation
GCC compiler can generate 8-bit stores when modifying bitfields of
volatile structs (https://github.com/espressif/esp-idf/issues/597).
In the specific case of I2C driver, this resulted in byte_num field
to be written using s8i. However the peripheral requires 32-bit
writes, and ignores 8-bit writes. This change modifies the code to
compose the 32-bit command register value first, and then write the
complete value to the hardware.
2019-03-18 18:23:50 +08:00
Sachin Parekh
d0234ad24a I2C: Enable Power Management locks
Acquires PM_APB_FREQ_MAX lock when carrying any transaction on I2C if
Power Management Framework is enabled.

Signed-off-by: Sachin Parekh <sachin.parekh@espressif.com>
2019-03-18 08:21:21 +00:00
Wangjialin
924daf7b84 bugfix(i2c): reduce speed of I2C master bus reset routine and release SDA
closes https://github.com/espressif/esp-idf/issues/2494
closes https://github.com/espressif/esp-idf/pull/2493
closes https://github.com/espressif/esp-idf/pull/2496

1. Change bus reset to handle interrupted READ sequences.
2. Slow down I2C to 100khz during reset
3. If a SLAVE device was in a read operation when the bus was interrupted, the SLAVE device is controlling SDA.The only bit during the 9 clock cycles of a byte READ the MASTER(ESP32) is guaranteed control over, is during the ACK bit period.
If the SLAVE is sending a stream of ZERO bytes, it will only release SDA during the ACK bit period. The master(ESP32) cannot generate a STOP unless SDA is HIGH. So, this reset code synchronizes the bit stream with, Either, the ACK bit, Or a 1 bit.
2018-11-30 10:08:28 +08:00
chuck todd
e55f9c1e98 1. Slow down I2C to 100khz During Reset
I am stealing this delay coding from @jeremyherbert #2493 pr.

2. Change Bus Reset to handle interrupted READ sequences.

The current code does not handle interrupted READ cycles.

 If a SLAVE device was in a read operation when the bus was interrupted, the SLAVE device is controlling SDA.

The only bit during the 9 clock cycles of a byte READ the MASTER(ESP32) is guaranteed control over, is during the ACK bit period.

If the SLAVE is sending a stream of ZERO bytes, it will only release SDA during the ACK bit period. The master(ESP32) cannot generate a STOP unless SDA is HIGH.

So, this reset code synchronizes the bit stream with, Either, the ACK bit, Or a 1 bit.

3. fix typo

correct `sda_id` to `sda_io` in `i2c_master_clear_bus()` @ryan-ma found it.  This typo was generated when I manually edited this patch on GitHub, I should have done a Copy/Paste operation!
2018-11-30 10:08:28 +08:00
jeremy
34c1d25c7f reduce speed of i2c master bus reset routine and release sda 2018-11-30 10:08:28 +08:00
morris
2b165f99c4 i2c_tool: add i2c_tool example test
1. add example test for i2c-tools
2. make command line arguments number configurable
2018-11-30 10:08:28 +08:00
kooho
33138a3dec driver(i2c): enable I2C master hardware filter by default. 2018-11-23 10:27:59 +08:00
Angus Gratton
a67d5d89e0 Replace all DOS line endings with Unix
Command run was:
git ls-tree -r HEAD --name-only | xargs dos2unix
2018-07-12 19:10:37 +08:00
kooho
f6f9f93a9d driver(i2c, rmt):Add intr_flag setting to ESP_INTR_FLAG_IRAM support when enable psram. 2018-05-21 09:37:56 +08:00
kooho
37db055cff driver(i2c): Fixed ack_err interrupt can't exit bug. 2018-03-26 16:31:17 +08:00
Per Malmberg
5fb16d9b2b Fix regression in i2c_master_read() which rejected all data lenths. 2017-12-28 14:54:15 +01:00
kooho
d78be97154 add NACK for the last byte to read 2017-12-26 21:50:18 +08:00
Angus Gratton
661d584ae7 Merge branch 'bugfix/i2c_fixes_pr1180' into 'master'
i2c: rx <-> tx typo's, NULLing free'd variable, consistent CRITICAL sects

See merge request !1551
2017-12-18 06:44:33 +08:00
Chuck Todd
d913fff6d7 i2c: rx <-> tx typo's, NULLing free'd variable, consistent CRITICAL sects
A couple of typos referencing tx_ring_buf when rx_ring_buf, slv_tx_mux
instead of slv_rx_mux.

Also, I2C_ENTER_CRITICAL()/I2C_EXIT_CRITICAL() usage was not consistent.
Only some of the _set_ functions had them.  Most of the _get_ function
had them?  It is my understanding that they should be wrapped around
writes, not reads? (I think we still need the lock for reading pairs of consistent values)

Also, the ticks_to_wait timeout handling in i2c_master_cmd_begin() would
not handle integer rollover correctly.

Merges https://github.com/espressif/esp-idf/pull/1180
2017-12-11 11:08:39 +08:00
Fabiano Kovalski
9075b507b5 driver(i2c): corrected timeout range for i2c_set_timeout.
Merges https://github.com/espressif/esp-idf/pull/1353
2017-12-08 14:26:35 +08:00
Wangjialin
bf3c41bb92 bugfix(i2c): use queue instead of event group for internal commands
Reported from github:
https://github.com/espressif/esp-idf/issues/1312
https://github.com/espressif/esp-idf/issues/1193

Issues:
1. We used to use event group in the driver, which would cause:
    a. longer operation time since the event group are based on FreeRTOS timer.
    b. Operation fails if the timer queue is not long enough.
2. There might be some issue with event group, we will still try to provide a small test code in other branch.

modification:
1. use queue instead of event-bit for internal commands
2. use queue overwrite for cmd_done event
2017-11-29 12:33:11 +08:00
Wangjialin
ed1e32f583 bugfix(i2c): add I2C hardware reset if the hw FSM get stuck
Reported from different sources from github or bbs:

https://github.com/espressif/esp-idf/issues/680

https://github.com/espressif/esp-idf/issues/922

We tested reading several sensor or other I2C slave devices, if the power and SDA/SCL wires are in proper condition, everything works find with reading the slave.
If we remove the power supply for the slave during I2C is reading, or directly connect SDA or SCL to ground, this would  cause the I2C FSM get stuck in wrong state, all we can do is the reset the I2C hardware in this case.
After this commit, no matter whether the power supply of I2C slave is removed or SDA / SCL are shorted to ground, the driver can recover from wrong state.

We are not sure whether this the save issue with the reported one yet, but to make the driver more robust.

Further information:

1. For I2C master mode, we have tested different situations, e.g., to short the SDA/SCL directly to GND/VCC, to short the SDA to SCL, to un-plug the slave device, to power off the slave device. Under all of those situations, this version of driver can recover and keep working.
2. Some slave device will die by accident and keep the SDA in low level, in this case, master should send several clock to make the slave release the bus.
3. Slave mode of ESP32 might also get in wrong state that held the SDA low, in this case, master device could send a stop signal to make esp32 slave release the bus.

Modifications:

1. Disable I2C_MASTER_TRAN_COMP interrupt to void extra interrupt.
2. Disable un-used timeout interrupt for slave.
3. Add bus reset if error detected for master mode.
4. Add bus clear if SDA level is low when error detected.
5. Modify the argument type of i2c_set_pin.
6. add API to set timeout value
7. add parameter check for timing APIs
2017-10-21 02:10:59 +08:00
Angus Gratton
a89e93fc3d i2c driver: When deleting, disable interrupts before freeing data structures
Fixes a potential race if I2C interrupt occurs while driver is being delted.
2017-06-08 15:57:31 +10:00
jack
fc130fba86 fix bug that files missing commit in MR 773 2017-05-31 19:37:39 +08:00
Michel Pollet
349a77cb55 components/driver: 'const' all config calls.
Some were, some weren't. They all could/should be.

Signed-off-by: Michel Pollet <buserror@gmail.com>
2017-04-13 18:33:33 +01:00
Ivan Grokhotkov
91d35f01f2 Merge branch 'bugfix/i2c_spikes_on_master_init_#393_from_github' into 'master'
bugfix: I2C spikes on master init

Fix I2C spikes on master init.
Before I2C io init, set high level on SDA/SCK IOs.

Fixes https://github.com/espressif/esp-idf/issues/393

See merge request !593
2017-03-21 15:09:16 +08:00
Wangjialin
1ad68de8b8 bugfix: I2C spikes on master init #393 from github
Fix I2C spikes on master init.
This issue is reported from https://github.com/espressif/esp-idf/issues/393
Before I2C io init, set high level on SDA/SCK IOs.
2017-03-19 17:05:07 +08:00
Wangjialin
94b91ee4af bugfix: i2c driver not working in 'RELEASE' configuration
This issue is reported from https://github.com/espressif/esp-idf/issues/304.
We found that when we operate the hw command registers in I2C struct, sometimes the behaviour would be different in DEBUG/RELEASE optimisation level:

The code looks like this:
I2C[i2c_num]->command[p_i2c->cmd_idx].byte_num -= 0;

In DEBUG configuration:
I2C[i2c_num]->command[p_i2c->cmd_idx].byte_num -= 0;
400f3ab0:    3388          l32i.n    a8, a3, 12
400f3ab2:    14c882            addi    a8, a8, 20
400f3ab5:    a08840            addx4    a8, a8, a4
400f3ab8:    0020c0            memw
400f3abb:    2898          l32i.n    a9, a8, 8
400f3abd:    0020c0            memw
400f3ac0:    28b8          l32i.n    a11, a8, 8
400f3ac2:    74a090            extui    a10, a9, 0, 8
400f3ac5:    00af92            movi    a9, 0xffffff00
400f3ac8:    109b90            and    a9, a11, a9
400f3acb:    2099a0            or    a9, a9, a10
400f3ace:    0020c0            memw
400f3ad1:    2899          s32i.n    a9, a8, 8

In RELEASE configuration:
I2C[i2c_num]->command[p_i2c->cmd_idx].byte_num -= 0;
400f2ba2:    580572            l8ui    a7, a5, 88
400f2ba5:    747070            extui    a7, a7, 0, 8
400f2ba8:    0020c0            memw
400f2bab:    584572            s8i    a7, a5, 88

Looks like the compiler will make it a 8bit operation after optimisation.
But the register value changes from 0x901 to 0x101.
After this 8-bit optimisation, the 11th bit changed from 1 to zero, which caused this error.

We are still trying to find out why that happens, because there might be some risk when operating the register struct.
This is a workaround to avoid "-=" operation on I2C register struct fields.
2017-03-19 16:09:44 +08:00