Omar Chebib
c218f669ba
panic on RISC-V: Take into account Merge Request comments
2020-12-31 15:46:17 +08:00
Omar Chebib
a90dcfba1a
panic: Add support for SoC-level panic
...
Activate "invalid access to cache raises panic (PRO CPU)" CI unit
test in order to test SoC-level panics.
2020-12-31 15:46:17 +08:00
Omar Chebib
b6a450f824
panic: Add support for SoC-level panic
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SoC level exceptions such as watchdog timer and cache errors are now supported.
Such exceptions now triggers a panic, giving more information about how
and when it happened.
2020-12-31 15:46:17 +08:00
Renz Bagaporo
4cc6b5571b
esp_system: support riscv panic
2020-11-13 07:49:11 +11:00
Angus Gratton
fccab8f4ef
riscv: Add new arch-level component
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Changes come from internal branch commit a6723fc
2020-11-12 09:33:18 +11:00