Commit Graph

54 Commits

Author SHA1 Message Date
Cao Sen Miao
3a4db97cec spi_flash: move patch files to common rom patch folder 2021-12-30 14:05:12 +08:00
Cao Sen Miao
56edc81b5d spi_flash: add support for th 1M flash 2021-12-13 11:47:48 +08:00
Omar Chebib
9d5923a13e IPC: Move ipc sources to esp_system
IPC shall be put back into esp_system as it is an 'OS additions'.
2021-11-11 10:30:01 +08:00
Ivan Grokhotkov
81b97b9a6b spi_flash: only add GCC-specific flags when building with GCC 2021-09-16 11:07:54 +02:00
Cao Sen Miao
6c0aebe279 esp_flash: add opi flash support in esp_flash chip driver, for MXIC 2021-09-07 14:44:40 +08:00
Jakob Hasse
46e59e7194 [mocks]: moved already added spi_flash mocks
[nvs]: page test works with new overriden mock

[spi_flash]: Removed mocking code from CMake

* Renamed nvs test to be consistent with other
  host test
2021-08-18 11:05:51 +08:00
Jakob Hasse
7029f0537e [build system]: Fixed common requirement for Linux 2021-08-13 16:50:29 +08:00
Jakob Hasse
0b86f81847 [nvs]: use real esp_common on host tests 2021-08-03 19:47:17 +08:00
Renz Bagaporo
7c22cccb9c esp32: cleanup build script 2021-07-16 20:14:27 +08:00
Renz Bagaporo
844af01eb4 esp32: move spiram, himem 2021-07-16 20:14:26 +08:00
Armando
bc248278f8 spiflash: add octal spi psram support on 727 2021-06-25 19:41:57 +08:00
Michael (XIAO Xufeng)
26585b4b4b esp_flash: support override default chip driver list 2021-04-26 16:05:42 +08:00
Jakob Hasse
68393c41c4 doc: linux host test documentation 2021-04-23 09:27:35 +08:00
Cao Sen Miao
f3e79ca166 spi_flash(c3): add boya chip support for suspend feature 2021-01-25 11:14:06 +08:00
Angus Gratton
d4c9a45675 spi_flash: Add ESP32-C3 support
Based on internal commit 3ef01301fff
2020-12-17 15:34:13 +11:00
Jakob Hasse
00819a3022 NVS flash: host-based unit test of nvs::Page
* General tests like page loading from flash
* Rough test of fixed-size data types
* Rough test of blob read
* Added coverage target in cmake, also accessible
  via `idf.py coverage`
* Fixed unsigned comparison in comp. enum table
* introducing temporary LINUX_TARGET define
2020-12-14 18:53:14 +08:00
Jakob Hasse
c233ce0449 spi_flash: mocking should be possible now
The following three headers will be mockes:
* esp_flash.h
* esp_spi_flash.h
* esp_partition.h
* counter functions live in own header
* add spi_flash sim dir for esp_err.h to Unity
* modified gen_esp_err_to_name.py to ignore
  sim/ dir in spi_flash component

Add cmock .yaml config file
Add spi hal header until soc can mock the hal
  layer as well.
2020-12-14 18:53:14 +08:00
Cao Sen Miao
11188d2143 esp_flash:fix bug about clearing WLE automatically after actions 2020-11-12 16:44:29 +08:00
Angus Gratton
e82eac4354 cmake: Apply cmakelint fixes 2020-11-11 07:36:35 +00:00
Michael (XIAO Xufeng)
3bacf35310 esp_flash: support high capacity flash chips (32-bit address) 2020-10-29 18:20:11 +08:00
Michael (XIAO Xufeng)
fefdee1349 bootloader: fix the WRSR format for ISSI flash chips
1. The 2nd bootloader always call `rom_spiflash_unlock()`, but never help to clear the WEL bit when exit. This may cause system unstability.

   This commit helps to clear WEL when flash configuration is done.

   **RISK:** When the app starts, it didn't have to clear the WEL before it actually write/erase. But now the very first write/erase operation should be done after a WEL clear. Though the risk is little (all the following write/erase also need to clear the WEL), we still have to test this carefully, especially for those functions used by the OTA.

2. The `rom_spiflash_unlock()` function in the patch of ESP32 may (1) trigger the QPI, (2) clear the QE or (3) fail to unlock the ISSI chips.

   Status register bitmap of ISSI chip and GD chip:

| SR | ISSI | GD25LQ32C |
| -- | ---- | --------- |
| 0  | WIP  | WIP       |
| 1  | WEL  | WEL       |
| 2  | BP0  | BP0       |
| 3  | BP1  | BP1       |
| 4  | BP2  | BP2       |
| 5  | BP3  | BP3       |
| 6  | QE   | BP4       |
| 7  | SRWD | SRP0      |
| 8  |      | SRP1      |
| 9  |      | QE        |
| 10 |      | SUS2      |
| 11 |      | LB1       |
| 12 |      | LB2       |
| 13 |      | LB3       |
| 14 |      | CMP       |
| 15 |      | SUS1      |

   QE bit of other chips are at the bit 9 of the status register (i.e. bit 1 of SR2), which should be read by RDSR2 command.

   However, the RDSR2 (35H, Read Status 2) command for chip of other vendors happens to be the QIOEN (Enter QPI mode) command of ISSI chips. When the `rom_spiflash_unlock()` function trys to read SR2, it may trigger the QPI of ISSI chips.

   Moreover, when `rom_spiflash_unlock()` try to clear the BP4 bit in the status register, QE (bit 6) of ISSI chip may be cleared by accident. Or if the ISSI chip doesn't accept WRSR command with argument of two bytes (since it only have status register of one byte), it may fail to clear the other protect bits (BP0~BP3) as expected.

   This commit makes the `rom_spiflash_unlock()` check whether the vendor is issi. if so, `rom_spiflash_unlock()` only send RDSR to read the status register, send WRSR with only 1 byte argument, and also avoid clearing the QE bit (bit 6).

3. `rom_spiflash_unlock()` always send WRSR command to clear protection bits even when there is no protection bit active. And the execution of clearing status registers, which takes about 700us, will also happen even when there's no bits cleared.

   This commit skips the clearing of status register if there is no protection bits active.

Also move the execute_flash_command to be a bootloader API; move
implementation of spi_flash_wrap_set to the bootloader
2020-09-19 10:51:51 +08:00
Michael (XIAO Xufeng)
5425ef4ee4 hal: extract hal component from soc component 2020-09-01 13:25:32 +08:00
Darian Leung
11d96b39d0 esp_ipc: Move to new component
This commit moves esp_ipc into a separate component.
2020-05-18 16:51:45 +08:00
Angus Gratton
dbdce93d23 spi_flash: Use per-chip flash_ops files for legacy API
Looks like when ESP32-S2 Beta support was merged, the separate files
were dropped by accident.
2020-04-24 12:43:47 -03:00
Michael (XIAO Xufeng)
3b429766bc esp_flash: support MXIC flash chips
The default chip driver (chip_generic) use command 01H + 2 bytes to
clear the QE bit. However this will accidently change the configuration
register value of the MXIC chip.

MXIC chip driver is added to fix that.
2020-04-01 20:54:23 +08:00
michael
7a3f21636f spi_flash: fix the reading issue using the ROM functions in the ROM 2020-02-26 11:12:09 +08:00
morris
e30cd361a8 global: rename esp32s2beta to esp32s2 2020-01-22 12:14:38 +08:00
Renz Christian Bagaporo
e6ad330018 ble_mesh_wifi_coexist example: Disable Wi-Fi RX IRAM optimisation
Otherwise IRAM usage is too high in this example.
2019-11-28 09:20:00 +08:00
wanglei
5e55ffc95a fix dummy issue in spi mem and make some spiflash api called from idf 2019-11-15 15:59:07 +00:00
Angus Gratton
894a3b4771 spi_flash: Remove duplicate spi_flash_rom_patch in CMakeLists.txt 2019-10-28 18:58:05 +11:00
Angus Gratton
8675a818f9 Merge branch 'master' into feature/esp32s2beta_merge 2019-10-22 13:51:49 +11:00
Michael (XIAO Xufeng)
eb104aa16f esp_flash: fix the quad issue for some GD flash chips
The GD flash with product ID 40H, is already used in Wrover-nosufix modules.
2019-10-14 17:25:59 +08:00
Michael (XIAO Xufeng)
571864e8ae esp_flash: fix set qe bit and write command issues
There used to be dummy phase before out phase in common command
transactions. This corrupts the data.

The code before never actually operate (clear) the QE bit, once it finds
the QE bit is set. It's hard to check whether the QE set/disable
functions work well.

This commit:

1. Cancel the dummy phase

2. Set and clear the QE bit according to chip settings, allowing tests
   for QE bits. However for some chips (Winbond for example), it's not
   forced to clear the QE bit if not able to.

3. Also refactor to allow chip_generic and other chips to share the same
   code to read and write qe bit; let common command and read command share
   configure_host_io_mode.

4. Rename read mode to io mode since maybe we will write data with quad
   mode one day.
2019-10-14 17:25:58 +08:00
Angus Gratton
adfc06a530 Merge branch 'master' into feature/esp32s2beta_merge 2019-09-20 10:28:37 +10:00
Michael (XIAO Xufeng)
6139864a4c esp_flash: fix coredump for legacy spi flash API
When legacy mode is used, the coredump still fails during linking
because "esp_flash_init_default_chip", "esp_flash_app_init" and
"esp_flash_default_chip " are not compiled and linked.

Instead of using ``if`` macros in callers, these functions are protected
by ``if`` macros in the header, and also not compiled in the sources.
"esp_flash_default_chip" variable is compiled with safe default value.
2019-09-14 16:56:31 +08:00
Michael (XIAO Xufeng)
9f1c8f0c76 spi_flash: support esp32s2beta 2019-09-04 10:53:25 +10:00
Angus Gratton
309376f51a spi_flash: Force legacy mode for ESP32-S2
Can be removed once IDF-763 is merged
2019-08-13 17:14:16 +10:00
Angus Gratton
04ae56806c Merge branch 'master' into feature/esp32s2beta_update 2019-08-08 15:26:58 +10:00
Angus Gratton
24d26fccde Merge branch 'master' into feature/esp32s2beta_update 2019-08-08 13:44:24 +10:00
Michael (XIAO Xufeng)
d6bd24ca67 esp_flash: add initialization interface for SPI devices 2019-06-27 13:27:27 +08:00
Renz Christian Bagaporo
9b350f9ecc cmake: some formatting fixes
Do not include bootloader in flash target when secure boot is enabled.
Emit signing warning on all cases where signed apps are enabled (secure
boot and signed images)
Follow convention of capital letters for SECURE_BOOT_SIGNING_KEY
variable, since it is
relevant to other components, not just bootloader.
Pass signing key and verification key via config, not requiring
bootloader to know parent app dir.
Misc. variables name corrections
2019-06-21 19:53:29 +08:00
Renz Christian Bagaporo
9eccd7c082 components: use new component registration api 2019-06-21 19:53:29 +08:00
Michael (XIAO Xufeng)
1036a091fe spi_flash: support working on differnt buses and frequency 2019-06-18 06:32:52 +00:00
Renz Christian Bagaporo
54ef60f26b component: revert some of the dependency corrections
!4452 and !4897 made some ill-advised corrections to dependency info;
revert those in this MR. Handling pre-built binaries as imported
libraries is retained, however.
2019-06-11 18:09:26 +08:00
suda-morris
84b2f9f14d build and link hello-world for esp32s2beta 2019-06-11 13:07:37 +08:00
suda-morris
61ce868396 make bootloader_support support esp32s2beta 2019-06-11 13:07:02 +08:00
Renz Christian Bagaporo
477fa49fc0 examples: update idf_as_lib example to use new api 2019-05-14 18:01:14 +08:00
Renz Christian Bagaporo
ffec9d4947 components: update with build system changes 2019-05-13 19:59:17 +08:00
Michael (XIAO Xufeng)
562af8f65e global: move the soc component out of the common list
This MR removes the common dependency from every IDF components to the SOC component.

Currently, in the ``idf_functions.cmake`` script, we include the header path of SOC component by default for all components.
But for better code organization (or maybe also benifits to the compiling speed), we may remove the dependency to SOC components for most components except the driver and kernel related components.

In CMAKE, we have two kinds of header visibilities (set by include path visibility):

(Assume component A --(depends on)--> B, B is the current component)

1. public (``COMPONENT_ADD_INCLUDEDIRS``): means this path is visible to other depending components (A) (visible to A and B)
2. private (``COMPONENT_PRIV_INCLUDEDIRS``): means this path is only visible to source files inside the component (visible to B only)

and we have two kinds of depending ways:

(Assume component A --(depends on)--> B --(depends on)--> C, B is the current component)

1. public (```COMPONENT_REQUIRES```): means B can access to public include path of C. All other components rely on you (A) will also be available for the public headers. (visible to A, B)
2. private (``COMPONENT_PRIV_REQUIRES``): means B can access to public include path of C, but don't propagate this relation to other components (A). (visible to B)

1. remove the common requirement in ``idf_functions.cmake``, this makes the SOC components invisible to all other components by default.
2. if a component (for example, DRIVER) really needs the dependency to SOC, add a private dependency to SOC for it.
3. some other components that don't really depends on the SOC may still meet some errors saying "can't find header soc/...", this is because it's depended component (DRIVER) incorrectly include the header of SOC in its public headers. Moving all this kind of #include into source files, or private headers
4. Fix the include requirements for some file which miss sufficient #include directives. (Previously they include some headers by the long long long header include link)

This is a breaking change. Previous code may depends on the long include chain.
You may need to include the following headers for some files after this commit:

- soc/soc.h
- soc/soc_memory_layout.h
- driver/gpio.h
- esp_sleep.h

The major broken include chain includes:

1. esp_system.h no longer includes esp_sleep.h. The latter includes driver/gpio.h and driver/touch_pad.h.
2. ets_sys.h no longer includes soc/soc.h
3. freertos/portmacro.h no longer includes soc/soc_memory_layout.h

some peripheral headers no longer includes their hw related headers, e.g. rom/gpio.h no longer includes soc/gpio_pins.h and soc/gpio_reg.h

BREAKING CHANGE
2019-04-16 13:21:15 +08:00
Renz Bagaporo
63411fc556 tools: implement linker script generation 2018-11-16 12:42:02 +08:00