Commit Graph

11 Commits

Author SHA1 Message Date
wuzhenghui
2302bc4862 fix(heap): fix memory caps defination in memory_layout
fix the issue on esp32c3 where retention memory was exhausted
prematurely and preventing the CPU from powering down because
all of the last level of RAM is retention dma accessible on
esp32c3.
2023-10-12 11:57:49 +08:00
KonstantinKondrashov
6d0d2366f7 esp_hw_support: Fix invalid system time if s_esp_rtc_time_us & s_rtc_last_ticks were moved around
The commit fixes the case:
If variables in RTC RAM have been moved around by the linker,
they will be filled with garbage data. Any reset other than OTA would work fine
because the variables would still be initialized from the initial bootup.

So now system time will be valid even after OTA.

Closes https://github.com/espressif/esp-idf/issues/9448
2023-06-26 18:12:30 +08:00
Guillaume Souchere
6382f28998 heap: Modify the memory type of the memory used as startup stack when memory protection is enabled
If memory protection is enabled on esp32c3 and esp32s3, we don't want to the heap component to see
the startup stack memory as D/IRAM but as DRAM only. Introduce a new type to make this possible in
the same fashion the regular D/IRAM regions are handled.
2023-01-26 10:52:34 +01:00
wuzhenghui
5e8ba9cea8 use enum and designated initializers in soc_memory_type define 2022-07-29 17:07:41 +08:00
wuzhenghui
7cb9304b65 Clean IRAM and DRAM address space conversion macros 2022-07-29 17:07:39 +08:00
wuzhenghui
65aea5d177 stack/dram is also IRAM0 accessible 2022-07-29 10:51:48 +08:00
wuzhenghui
21a4eda4d4 Use the entire sharedbuffer space as the heap of the D/IRAM attribute 2022-07-29 10:51:47 +08:00
Jing Li
a0e794b2ca heap: adjust the order of RTC memory heap caps and regions 2021-12-29 08:49:42 +00:00
Cao Sen Miao
a9f0a3531e ESP8684: add driver esp_pm heap support 2021-11-06 17:33:44 +08:00
wuzhenghui
ca1c4114bc heap: update esp32&s2&c3&h2 soc caps 2021-11-04 10:40:57 +08:00
Omar Chebib
c4f57af6c9 G0: Memory layouts are now part of heap components 2021-07-15 11:38:23 +10:00