A couple of typos referencing tx_ring_buf when rx_ring_buf, slv_tx_mux
instead of slv_rx_mux.
Also, I2C_ENTER_CRITICAL()/I2C_EXIT_CRITICAL() usage was not consistent.
Only some of the _set_ functions had them. Most of the _get_ function
had them? It is my understanding that they should be wrapped around
writes, not reads? (I think we still need the lock for reading pairs of consistent values)
Also, the ticks_to_wait timeout handling in i2c_master_cmd_begin() would
not handle integer rollover correctly.
Merges https://github.com/espressif/esp-idf/pull/1180
Reported from github:
https://github.com/espressif/esp-idf/issues/1312https://github.com/espressif/esp-idf/issues/1193
Issues:
1. We used to use event group in the driver, which would cause:
a. longer operation time since the event group are based on FreeRTOS timer.
b. Operation fails if the timer queue is not long enough.
2. There might be some issue with event group, we will still try to provide a small test code in other branch.
modification:
1. use queue instead of event-bit for internal commands
2. use queue overwrite for cmd_done event
Previously SDSPI host driver would rely on retry count when waiting for
the card to read or write data. This caused different timeout times
depending on CPU frequency and card clock frequency. In practice, card
performance does not depend on these two factors.
This change uses timeout_ms field of sdmmc_command_t introduced
previously for SDMMC host.
Fixes https://esp32.com/viewtopic.php?f=2&t=3440&p=16037 and similar
issues related to SDSPI timeouts.
1. All the registers of touch sensor 8 and 9 are mismatched except the ‘dac’ field in touch register of RTC IO
2. To swap the index for sensor 8 and 9 in APIs.
Reported from github:
https://github.com/espressif/esp-idf/issues/1219https://github.com/espressif/esp-idf/issues/1202
After providing a simple code to digital team, they confirmed that this is a hardware bug.
Root cause:
The fifo reset signal is incorrectly connected
If we want to reset tx fifo of UART2, we have to set txfifo_rst bit of both UART1 and UART2
If we want to reset rx fifo of UART2, we have to set rxfifo_rst bit of both UART1 and UART2
Workaround:
we don't use fifo rst bit in driver.
Documentation:
Digital team would update TRM and give more explanation about this issue.
1. move settings of WIFI_CLK_EN_REG for bluetooth into controller init/deinit APIs
2. modify the bit mask used in phy_rf init/deinit to use WIFI-BT shared bits
append adc support and api
- esp_err_t adc2_config_width(adc_bits_width_t width_bit);
- esp_err_t adc2_config_channel_atten(adc2_channel_t channel, adc_atten_t atten);
- int adc2_get_voltage(adc2_channel_t channel);
Reported from:
https://github.com/espressif/esp-idf/issues/703https://github.com/espressif/esp-idf/issues/917
In uart driver we didn't change the default value of tx idle num, so there would be a delay after tx FIFO is empty.
1. Add API to set tx idle interval before next data transmission. (The UART hardware can add an interval after tx FIFO is empty).
2. Set default tx idle interval to zero.
3. Add hardware disable in uart driver delete function.
