Commit Graph

205 Commits

Author SHA1 Message Date
wuzhenghui
8f78520342 esp_phy: only esp32c3&esp32s3 support MAC_BB_PD, remove unused caps define 2022-12-16 15:47:59 +08:00
wuzhenghui
5822cdf93b esp_phy: enable for esp32c6 2022-12-16 15:47:56 +08:00
wuzhenghui
b887f86a78 soc: add SOC_IEEE802154_SUPPORTED caps 2022-12-15 17:18:28 +08:00
Song Ruo Jing
9402ab427b ledc: Add basic support for esp32c6 2022-12-07 18:40:50 +08:00
C.S.M
6b1d4b4d49 ESP32-H2: Last MR for g0 component support, (only hal left) 2022-12-05 17:32:21 +08:00
Cao Sen Miao
5520e3b811 ESP32H2: Add SOC files for esp32h2 2022-11-29 18:55:12 +08:00
Cao Sen Miao
86aa4df5b5 ESP32-H2: Introduce new target for ESP32H2 2022-11-23 14:38:05 +08:00
laokaiyao
8677216576 esp32h2: renaming esp32h2 to esp32h4 2022-11-08 17:05:33 +08:00
morris
f69a53f56d Merge branch 'feature/twai_bringup_esp32c6' into 'master'
TWAI: initial driver bring up on esp32c6 (TWAI0 only)

Closes IDF-5313 and IDF-5940

See merge request espressif/esp-idf!20735
2022-11-07 18:00:05 +08:00
morris
a25123f703 twai: bringup on esp32c6 2022-11-04 17:40:29 +08:00
morris
6828c011d9 twai: define clock source name
twai clock source is target-specific,
this commit is to define them in the soc layer
2022-11-04 17:40:29 +08:00
laokaiyao
fa9b022f68 i2s: support 4 line pdm rx on esp32s3 2022-11-04 15:46:34 +08:00
laokaiyao
9b8a78153f i2s: refactor soc caps 2022-11-04 12:31:12 +08:00
Jiang Jiang Jian
f191b2f034 Merge branch 'bugfix/fix_xtal_related_rtc_params_for_esp32' into 'master'
esp32/rtc: fix xtal unstable in some cases when sleep

Closes ESPCS-869

See merge request espressif/esp-idf!20425
2022-10-26 15:57:48 +08:00
Song Ruo Jing
6d24e8bcf4 gpio: Add support for esp32c6 2022-10-18 12:38:36 +08:00
jingli
b903a2253b esp_hw_support/sleep: fix current leakage when hold digital io during deep sleep 2022-10-11 12:11:28 +08:00
jingli
0a44d09f4f esp32/rtc: fix xtal unstable in some cases when sleep
1. add xtal buf wait to fix high temperature restart issue
2. add min sleep value to fix xtal stop due to too short sleep time issue
2022-10-09 19:58:58 +08:00
jingli
05a2fbe810 esp_hw_support/clk_cali: fix xtal32k error detect 2022-09-21 03:03:25 +00:00
wangjialiang
6e79d05814 ble_mesh: docs: Remove BLE Mesh related reference for C2 2022-09-16 19:39:51 +08:00
Kevin (Lao Kaiyao)
04b4bc6cb5 Merge branch 'feature/support_i2s_on_esp32c6' into 'master'
i2s: support i2s on esp32c6

See merge request espressif/esp-idf!19989
2022-09-16 12:31:24 +08:00
laokaiyao
7197e987cb i2s: add XTAL clock source 2022-09-15 19:32:06 +08:00
Omar Chebib
53c7dd4efc WDT: implement interrupt wdt and task wdt for ESP32-C2
ESP32-C2 has a single group timer, thus it will use it for the interrupt watchdog,
which is more critical than the task watchdog. The latter is implement in
software thanks to the `esp_timer`component.
2022-09-15 14:37:59 +08:00
morris
5f550b2a13 rmt,gptimer: don't support rc_fast clock source for c6 and h2
The RC_FAST clock source on ESP32C6 and ESP32H2 can't be calibrated.
Which makes it impossible to work stable for peripherals like timer, RMT
2022-09-14 14:40:28 +00:00
wanlei
96aa2792f8 spi_master:fix error when use spi_bus_add_device more than 3 device
update gpio_sig at `spics_out` array in each spi_periph.c of chips later than s2
then `spi_bus_add_device` can correctly distribute gpio_signals for cs_signal

Closes https://github.com/espressif/esp-idf/issues/8876
2022-09-05 12:10:22 +08:00
songruojing
9d515185d0 esp32c6: clean up existing soc files and header file inclusion in IDF to be compatible with the new chip 2022-09-01 12:28:06 +08:00
Song Ruo Jing
6a60ecf780 soc_caps: Introduce SOC_LEDC_SUPPORTED and SOC_I2C_SUPPORTED caps to IDF
Wrap the ledc, i2c source files with the new caps in CMakeLists and linker.lf.
This could avoid potential source file not found warning during linking time.
2022-08-31 20:43:22 +08:00
Michael (XIAO Xufeng)
746f4b814c uart: move frequency of clock sources out of HAL 2022-08-15 18:55:43 +00:00
Geng Yuchao
0a1d8c1e09 Fix soc caps define for all chips 2022-08-08 20:50:28 +08:00
jingli
ee3423834e kconfig: refactor xtal freq kconfig to common configuration item 2022-08-05 19:12:29 +08:00
wuzhenghui
7cb9304b65 Clean IRAM and DRAM address space conversion macros 2022-07-29 17:07:39 +08:00
wuzhenghui
21a4eda4d4 Use the entire sharedbuffer space as the heap of the D/IRAM attribute 2022-07-29 10:51:47 +08:00
morris
d94432fea8 systimer: refactor hal to accomodate more xtal choices 2022-07-25 16:08:52 +08:00
morris
741b031e83 soc: added SOC_TOUCH_SENSE_SUPPORTED macro 2022-07-22 00:12:36 +00:00
laokaiyao
edee3ee3cd i2s: add slot sequence table
Closes: https://github.com/espressif/esp-idf/issues/9208

When I2S is configured into different modes, the slot sequence varies.
This commit updates slot sequence tables and corresponding descriptions
in (both code and programming guide).
2022-07-21 15:52:39 +08:00
laokaiyao
90866e99fb i2s: add basic examples for STD/TDM/PDM mode 2022-07-21 15:52:39 +08:00
morris
4154eaec93 sdm: clean up soc/hal/ll code 2022-07-20 14:59:50 +08:00
Song Ruo Jing
4734b1433b Merge branch 'bugfix/gpio_hal_coverity_fix' into 'master'
gpio: Fix ESP32S3 GPIO48 does not support hold function bug and Fix coverity report

Closes IDF-4901

See merge request espressif/esp-idf!18805
2022-07-19 21:37:15 +08:00
Armando (Dou Yiwen)
9f6f61345b Merge branch 'feature/adc_driver_ng' into 'master'
ADC Driver NG

Closes IDF-4560, IDF-3908, IDF-4225, IDF-2482, IDF-4111, IDF-3610, IDF-4058, IDF-3801, IDF-3636, IDF-2537, IDF-4310, IDF-5150, IDF-5151, and IDF-4979

See merge request espressif/esp-idf!17960
2022-07-19 21:28:31 +08:00
Cao Sen Miao
53580a62b5 I2C: Fullfill the I2C clock tree, and support 26M XTAL on ESP32-C2 2022-07-19 11:41:42 +08:00
Armando
5b523a3313 esp_adc: new esp_adc component and adc drivers 2022-07-15 18:31:00 +08:00
songruojing
145454356b gpio: Fix ESP32S3 GPIO48 does not support hold function bug
GPIO_HOLD_MASK array was missing the last item

Add __Static_assert to check array sizes for all gpio_periph.c files to prevent same mistake in the future.
2022-07-15 16:51:25 +08:00
Jiang Jiang Jian
3630713e5f Merge branch 'docs/esp32c2_sys_feature_api_guides' into 'master'
docs: update system API-guides for ESP32-C2

Closes IDF-4202, IDF-4213, and IDF-4222

See merge request espressif/esp-idf!18979
2022-07-12 10:59:12 +08:00
Marius Vikhammer
d62421619c docs: update system API-guides for ESP32-C2 2022-07-12 09:32:43 +08:00
songruojing
b3d8db3ae2 bootloader, esp_system: esp32c2 console uart to support 26MHz xtal
Gets the XTAL frequency from the RTC storage register, remove UART_CLK_FREQ_ROM macro from soc.h
2022-07-11 12:24:58 +08:00
Ivan Grokhotkov
5b54ae76d4 esp_timer, hal: add support for non-integer systimer frequency
When ESP32-C2 is paired with a 26 MHz XTAL, the systimer tick
frequency becomes equal to 26 / 2.5 = 10.4 MHz. Previously we always
assumed that systimer tick frequency is integer (and 1 MHz * power of
two, above that!).
This commit introduces a new LL macro, SYSTIMER_LL_TICKS_PER_US_DIV.
It should be set in such a way that:

1. SYSTIMER_LL_TICKS_PER_US / SYSTIMER_LL_TICKS_PER_US_DIV equals the
   actual systimer tick frequency,
2. and SYSTIMER_LL_TICKS_PER_US is integer.

For ESP32-C2 this means that SYSTIMER_LL_TICKS_PER_US = 52 and
SYSTIMER_LL_TICKS_PER_US_DIV = 5.

This introduced two possible issues:

1. Overflow when multiplying systimer counter by 5
   - Should not be an issue, since systimer counter is 52-bit, so
     counter * 5 is no more than 55-bit.
2. The code needs to perform:
   - divide by 5: when converting from microseconds to ticks
   - divide by 52: when converting from ticks to microseconds
   The latter potentially introduces a performance issue for the
   esp_timer_get_time function.
2022-07-11 12:24:37 +08:00
GengYuchao
d145c337e0 Enable rpa_moudle reset function 2022-07-05 20:50:31 +08:00
morris
7863c1bc45 Merge branch 'bugfix/fix_rtc_freq_err_for_h2_beta1' into 'master'
Bugfix/fix rtc freq err for h2 beta1

See merge request espressif/esp-idf!18682
2022-07-04 16:46:17 +08:00
Omar Chebib
cd48baf979 Refactor: move regi2c_*.h header files from esp_hw_support to soc component
When creating G0 layer, some regi2c_*.h headers were moved out from
esp_hw_support (G1) to soc (G0). In order to be consistent with that change,
move all the remaining regi2c_*.h headers to soc too.
2022-06-30 09:40:44 +00:00
GengYuchao
10fd1daa10 Add ETM clk gate defines for h2 2022-06-30 17:02:00 +08:00
Armando
31b3f31ef4 ext_mem: make memory region check strict 2022-06-28 14:17:44 +08:00