Ivan Grokhotkov
3323f31cfb
soc: implement XTAL frequency detection
...
ROM code already implements XTAL frequency detection, but it uses the 8M
clock before the clock tuning parameters are initialized. With the
zero clock tuning parameter, 8M clock has significant frequency deviation
at high temperatures, which can lead to erroneous detection of 40 MHz
crystal as a 26 MHz one.
This change adds XTAL frequency detection code to rtc_clk_init routine,
and detection is performed after the 8M clock tuning parameter as been
initialized.
2017-04-24 15:29:30 +08:00
Alexey Gerenkov
77a92e6dcc
esp32: Added dumping info from traceport upon reset by any WDT
...
- Last PC info and waiti mode indication are printed for both CPUs
- Raw traceport regs values are printed only for log levels higher than DEBUG
2017-04-23 22:07:56 +03:00
Ivan Grokhotkov
5d1bb42c18
soc: allow REG_SET_FIELD to be used with single-bit fields
2017-04-18 17:34:26 +08:00
Ivan Grokhotkov
faaf59ccb3
soc: define missing M, V macros for nrx, bb, fe, emac, iomux
...
Recipe:
- Add _M and _V for single-bit fields
Search: (#define (\w+)\s*(\(BIT\(\d+\)\)))
Replace: \1\n#define \2_M \3\n#define \2_V 1
- Add _M and _V for multi-bit fields
Search: (#define (\w+)\s*(0x[\dA-Fa-f]+))
Replace: \1\n#define \2_M (\2_V << \2_S)\n#define \2_V \3
2017-04-18 17:34:26 +08:00
Jeroen Domburg
0b79d07d34
add detection of invalid cache access
...
- fix level 4 interrupt vectors to produce correct backtrace
- initialize invalid cache access interrupt on startup
- handle invalid cache access in panic handler
2017-04-13 15:27:38 +08:00
Ivan Grokhotkov
3c6c1e36ec
soc: add invalid cache access interrupt bits to dport_reg
2017-04-13 15:27:38 +08:00
Ivan Grokhotkov
7ee8ee8b7e
soc: add source code of rtc_clk, rtc_pm
2017-04-11 15:45:54 +08:00
Ivan Grokhotkov
9ff446e6f9
soc: convert line endings to unix
2017-04-11 15:44:22 +08:00
Ivan Grokhotkov
d6dbf15a1f
soc: move header files into soc component
2017-04-11 14:06:40 +08:00
