Commit Graph

448 Commits

Author SHA1 Message Date
Michael (XIAO Xufeng)
17b9cc6b4a pm: fixed RTC8M domain power issues
introduced in e44ead5356

1. The int8M power domain config by default is PD. While LEDC is using
RTC8M as clock source, this power domain will be kept on.

But when 8MD256 is used as RTC clock source, the power domain should
also be kept on.

On ESP32, there was protection for it, but broken by commit
e44ead5356. Currently the power domain
will be forced on when LEDC is using RTC8M as clock source &&
!int8m_pd_en (user enable ESP_PDP_DOMAIN_RTC8M in lightsleep). Otherwise
the power domain will be powered off, regardless of RTC clock source.

In other words, int8M domain will be forced off (even when 8MD256
used as RTC clock source) if LEDC not using RTC8M as clock source, user
doesn't enable ESP_PDP_DOMAIN_RTC8M, or in deep sleep.

On later chips, there's no such protection, so 8MD256 could't be used as
RTC clock source in sleep modes.

This commit adds protection of 8MD256 clock to other chips. Fixes the
incorrect protection logic overriding on ESP32. Now the power domain
will be determiend by the logic below (order by priority):

    1. When RTC clock source uses 8MD256, power up
    2. When LEDC uses RTC8M clock source, power up
    3. In deepsleep, power down
    4. Otherwise determined by user config of ESP_PDP_DOMAIN_RTC8M,
       power down by default. (This is preferred to have highest
       priority, but it's kept as is because of current code structure.)

2. Before, after the macro `RTC_SLEEP_CONFIG_DEFAULT` decides dbias, the
protection above may force the int8m PU. This may cause the inconsistent
of dbias and the int8m PU status.

This commit lifts the logic of pd int8m/xtal fpu logic to upper layer
(sleep_modes.c).

Related: https://github.com/espressif/esp-idf/issues/8007, https://github.com/espressif/esp-idf/pull/8089

temp
2022-05-12 15:57:09 +08:00
morris
3e7448d0f3 i80_lcd: support I2S1 LCD mode for esp32 2022-04-19 13:01:13 +00:00
songruojing
bdd7610e66 uart: fixed incorrect channel number on ESP32S2, S3 and C3 2022-03-02 02:42:06 +08:00
Michael (XIAO Xufeng)
c2c4b126f7 Merge branch 'feature/support_new_psram_v4.4' into 'release/v4.4'
psram: add ESP32-D0WD-R2-V3 support(backport v4.4)

See merge request espressif/esp-idf!16705
2022-02-13 14:13:38 +00:00
Roland Dobai
a59e3ab59d Merge branch 'feature/esp32s3_apptrace_v4.4' into 'release/v4.4'
Feature/esp32s3 apptrace v4.4

See merge request espressif/esp-idf!16649
2022-01-26 09:58:35 +00:00
laokaiyao
816b0ce878 i2s: impove the apll and clock division calculation 2022-01-13 11:06:40 +08:00
Cao Sen Miao
e2ef65e117 psram: add ESP32-D0WD-R2-V3 support 2022-01-10 10:39:00 +08:00
Alexey Gerenkov
8c2990fcea trax: Adds ESP32-S3 support 2022-01-05 19:34:28 +01:00
Armando
1ec46ad3b8 adc: support adc dma driver on all chips 2021-12-23 17:13:46 +08:00
weitianhua
1383785aa1 Remove dummy defines of Classic BT 2021-10-29 14:21:26 +08:00
weitianhua
f4aad85f8b Make Classic BT related document links only visible for ESP32 2021-10-29 14:21:12 +08:00
Kevin (Lao Kaiyao)
a9faafee3c Merge branch 'feature/touch_sensor_driver_support_for_esp32s3' into 'master'
driver(touch): support touch sensor for esp32s3 platform

Closes IDF-1784 and IDF-3302

See merge request espressif/esp-idf!14102
2021-10-12 05:50:58 +00:00
laokaiyao
f4705f8eb4 touch sensor: update copyright notice 2021-10-08 11:45:57 +08:00
laokaiyao
a1cadba191 touch_sensor: apply general check 2021-10-08 11:32:12 +08:00
fuzhibo
589646a31e update touch with review advice 2021-10-08 10:39:46 +08:00
fuzhibo
057b9d61b5 driver(touch): support touch sensor for esp32s3 platform 2021-10-08 10:39:46 +08:00
morris
e09e39c94f lcd: unify callback prototype 2021-10-02 14:23:31 +08:00
Jiang Jiang Jian
f5ae8b0533 Merge branch 'feature/ledc_use_rtc8m_or_xtal_lightsleep' into 'master'
support RTC8M and XTAL power domain in light sleep mode

Closes IDF-3419

See merge request espressif/esp-idf!15152
2021-09-27 04:02:29 +00:00
Li Shuai
f5b39a7cde esp_hw_support: No voltage drop during light sleep to ensure stable output clock of rtc8m oscillator 2021-09-16 14:40:46 +08:00
Armando
c45c6f52f1 adc: support adc efuse-based calibration on esp32s3 2021-09-14 11:42:50 +08:00
Li Shuai
e44ead5356 Power Management: add RTC8M power domain to control whether internal 8m oscillator is powered down during sleep 2021-09-13 17:36:54 +08:00
morris
9d97d01679 Merge branch 'bugfix/mcpwm_cpp_reserved_word' into 'master'
bugfix/mcpwm: rename invalid keyword 'operator'

Closes IDFGH-5840

See merge request espressif/esp-idf!15159
2021-09-13 03:10:04 +00:00
SalimTerryLi
d9f4ae02f1
mcpwm: rename keyword 'operator' which is not valid in cpp
Closes https://github.com/espressif/esp-idf/issues/7542
2021-09-10 12:41:42 +08:00
baohongde
006a10b050 components/doc: Update doc about high-level interrupt
some bugfix.
2021-09-09 20:40:09 +08:00
baohongde
6d63fe06fa components/os: add config option to choose system check intterupt level. 2021-09-09 11:29:12 +08:00
baohongde
d1db2df316 components/bt: High level interrupt in bluetooth
components/os: Move ETS_T1_WDT_INUM, ETS_CACHEERR_INUM and ETS_DPORT_INUM to l5 interrupt

components/os: high level interrupt(5)

components/os: hli_api: meta queue: fix out of bounds access, check for overflow

components/os: hli: don't spill registers, instead save them to a separate region

Level 4 interrupt has a chance of preempting a window overflow or underflow exception.
Therefore it is not possible to use standard context save functions,
as the SP on entry to Level 4 interrupt may be invalid (e.g. in WindowUnderflow4).

Instead, mask window overflows and save the entire general purpose register file,
plus some of the special registers.
Then clear WindowStart, allowing the C handler to execute without spilling the old windows.
On exit from the interrupt handler, do everything in reverse.

components/bt: using high level interrupt in lc

components/os: Add DRAM_ATTR to avoid feature `Allow .bss segment placed in external memory`

components/bt: optimize code structure

components/os: Modify the BT assert process to adapt to coredump and HLI

components/os: Disable exception mode after saving special registers

To store some registers first, avoid stuck due to live lock after disabling exception mode

components/os: using dport instead of AHB in BT to fix live lock

components/bt: Fix hli queue send error

components/bt: Fix CI fail

# Conflicts:
#	components/bt/CMakeLists.txt
#	components/bt/component.mk
#	components/bt/controller/bt.c
#	components/bt/controller/lib
#	components/esp_common/src/int_wdt.c
#	components/esp_system/port/soc/esp32/dport_panic_highint_hdl.S
#	components/soc/esp32/include/soc/soc.h
2021-09-09 11:29:06 +08:00
laokaiyao
c5afd7ce34 i2s: fix write failure on ESP32 in 32bit slave mode 2021-09-03 17:36:44 +08:00
laokaiyao
b26da6f115 driver/i2s: refactor for i2s driver layer 2021-09-02 14:33:36 +08:00
SalimTerryLi
874a720286
soc/ll: workaround compiler bug that generate 8/16 bits inst instead of 32 bits one
update all struct headers to be more "standardized":

- bit fields are properly wrapped with struct
- bitwidth sum should be 32 within same struct, so that it's correctly padded with reserved bits
- bit field should be uint32_t
- typedef volatile struct xxx{} yyy;: xxx must exists. refer: https://github.com/espressif/esp-idf/pull/3199

added helper macros to force peripheral registers being accessed in 32 bitwidth

added a check script into ci
2021-08-30 13:50:58 +08:00
Michael (XIAO Xufeng)
375145ecdb Merge branch 'feature/mcpwm_bldc_hall_example' into 'master'
mcpwm: bldc hall example

Closes IDF-3648

See merge request espressif/esp-idf!14578
2021-08-26 08:28:27 +00:00
Song Ruo Jing
fe5c87cb3c Merge branch 'bugfix/enable_gpio_20' into 'master'
gpio: Enable IO20 on ESP32

Closes IDFGH-5140

See merge request espressif/esp-idf!14881
2021-08-25 07:25:37 +00:00
morris
3bfd8f5d5f mcpwm: update register file according to TRM 2021-08-24 15:38:46 +08:00
Alberto García Hierro
6deaefde69 Enable IO20 on ESP32
Some newer ESP32 variants (like ESP32-PICO-V3 and ESP32-PICO-MINI-02)
do implement this pin and it can be used as a normal GPIO.

Fixes #6016
Fixes #6837

Closes https://github.com/espressif/esp-idf/pull/6918
2021-08-20 14:05:38 +08:00
morris
bb87fd8f08 Merge branch 'refactor/pcnt_driver_esp32s3' into 'master'
pcnt: soc update and hal refactor

See merge request espressif/esp-idf!14698
2021-08-20 04:23:15 +00:00
morris
6fdc5877cd lcd: support i80 LCD on esp32/s2/s3 2021-08-10 21:06:59 +08:00
morris
1656cee69d i2s: correct soc info
1. remove non-exist I2S instance
2. update soc_caps.h, i2s_ll.h
2021-08-10 21:06:59 +08:00
suda-morris
9920271c21 pcnt: update pcnt soc data for all targets 2021-08-10 17:19:21 +08:00
Wang Meng Yang
8652b1d576 Merge branch 'bugfix/btdm_esp32_ble_white_list_connection_fail' into 'master'
Fixed ESP32 BLE can't resolve the peer address when enable white list

See merge request espressif/esp-idf!14348
2021-08-09 06:46:08 +00:00
Michael (XIAO Xufeng)
947980ecac Merge branch 'bugfix/uart_set_pin_use_iomux' into 'master'
uart: uart_set_pin function will now use IOMUX whenever possible

Closes IDF-3183

See merge request espressif/esp-idf!14318
2021-08-05 04:17:29 +00:00
xiewenxiang
1cc0f6aac5 Fixed ESP32 BLE can't resolve the peer address when enable white list 2021-08-04 22:00:38 +08:00
Omar Chebib
779e7400b0 uart: uart_set_pin function will now use IOMUX whenever possible
By using IOMUX instead of GPIO Matrix for UART, it is now possible
on ESP32 boards to use the UART as a wake up source even if it is
not used as a console.
For other boards where this issue was not present, using IOMUX has
the advantage to be faster than using GPIO matrix, so a highest
baudrate can be used
2021-08-04 12:48:30 +08:00
laokaiyao
f863998e90 driver/i2s: support mclk 2021-08-04 10:20:03 +08:00
laokaiyao
d51b85989b doc/i2s: update i2s programming guide on s3 & c3 2021-08-04 10:20:03 +08:00
houwenxiang
2f1247e1c4 driver: support I2S on ESP32-S3 & ESP32-C3
1. refactor I2S driver.
  2. support TDM mode for esp2s3 & esp32c3.
2021-08-04 10:20:03 +08:00
Konstantin Kondrashov
4972605b16 esp_common: Add API for IPC to run small pieces of code on the other CPU, in the context of the level 4 interrupt 2021-08-03 14:35:29 +08:00
morris
88c87bfe56 mcpwm: update hal and soc naming 2021-07-26 22:32:45 +08:00
Li Hang Fan
61f79cbf9c Merge branch 'refactor/move_ldscript_to_soc' into 'master'
refactor/soc: Move peripheral linker scripts out of target component

Closes IDF-3580

See merge request espressif/esp-idf!14474
2021-07-23 11:54:56 +00:00
SalimTerryLi
2347e68e6b
soc: move peripheral linker scripts out of target component 2021-07-22 12:55:01 +08:00
Omar Chebib
c4f57af6c9 G0: Memory layouts are now part of heap components 2021-07-15 11:38:23 +10:00
morris
1560d6f1ba soc: add reset reasons in soc component 2021-07-13 10:45:38 +08:00