Commit Graph

117 Commits

Author SHA1 Message Date
Marius Vikhammer
eb788deb03 esp_hw_support: merge C3 changes to master
Merge RTC related C3 changes to master
2020-12-30 12:20:41 +08:00
Angus Gratton
629b4270b4 Merge branch 'feature/c3_mbedtls_merge' into 'master'
mbedtls: merge changes from C3 to master

Closes IDF-2544 and IDF-2114

See merge request espressif/esp-idf!11718
2020-12-29 12:37:08 +08:00
Angus Gratton
1b0442b963 Merge branch 'feature/unify_rtc_fast_mem_as_heap_config_across_chips' into 'master'
esp_system: make rtc fast memory to heap configuration unified across chips

Closes IDF-2503

See merge request espressif/esp-idf!11693
2020-12-29 11:41:05 +08:00
Marius Vikhammer
1b6891c5d8 mbedtls: merge changes from C3 2020-12-29 10:56:13 +08:00
Mahavir Jain
880a63b2e9 esp_system: make rtc fast memory to heap configuration unified across chips
Closes IDF-2503
2020-12-24 09:46:35 +05:30
Angus Gratton
ed737becde soc: Move esp32c3 soc_memory_layout.c to soc component
Was incorrectly placed in esp_hw_support
2020-12-24 13:40:01 +11:00
Angus Gratton
b7f4c46a82 soc: Update esp32c3 soc headers
From internal commit 6d894813
2020-12-24 10:47:34 +11:00
Angus Gratton
6d6510c39b soc: Move esp32c3 soc_memory_layout.c to soc component
Was incorrectly placed in esp_hw_support
2020-12-23 11:49:16 +11:00
Armando
2d37bfa126 driver: Add adc_digi single conversion mode
- add lock for single read and continuous read APIs
- update onetime read start singal delay for hardware limitation[*]
- move adc_caps to soc_caps.h
- update license dates

[*] There is a hardware limitation. If the APB clock frequency is high, the
step of this reg signal: ``onetime_start`` may not be captured by the
ADC digital controller (when its clock frequency is too slow). A rough
estimate for this step should be at least 3 ADC digital controller
clock cycle.
2020-12-23 09:53:24 +11:00
Angus Gratton
fa892eb017 soc: Explain units for rtc_clk_cal() function, fix typo 2020-12-23 09:53:24 +11:00
Cao Sen Miao
e338a2e3df rtc: add function to en/disable the rtc clock 2020-12-23 09:53:24 +11:00
Angus Gratton
f09b8ae7a4 driver: Add esp32c3 ADC driver
Based on internal commit 3ef01301fffa552d4be6d81bc9d199c223224305
2020-12-23 09:53:24 +11:00
Angus Gratton
27a9cf861e driver: Add esp32c3 drivers (except ADC/DAC) and update tests
Some ESP32-C3 drivers are still pending.

Based on internal commit 3ef01301fffa552d4be6d81bc9d199c223224305
2020-12-23 09:53:24 +11:00
Cao Sen Miao
0736c91d68 soc: Remove cache constants from soc.h 2020-12-17 15:34:13 +11:00
Marius Vikhammer
457ce080ae AES: refactor and add HAL layer
Refactor the AES driver and add HAL, LL and caps.

Add better support for running AES-GCM fully in hardware.
2020-12-10 09:04:47 +00:00
Armando
d393699ab6 uart: bringup on esp32c3 2020-11-30 15:23:15 +11:00
Angus Gratton
c29d93986d soc: Add initial ESP32-C3 support
From internal commit 7761d6e8
2020-11-30 11:12:56 +11:00