6 Commits

Author	SHA1	Message	Date
Omar Chebib	102d5bbf72	refactor(riscv): added a new API for the interrupts	2024-01-18 16:36:53 +08:00
Omar Chebib	8ca191e4c1	fix(esp32p4): Fixed interrupt handling to use the CLIC controller	2023-08-31 12:16:08 +08:00
Armando	019e68bb15	feat(interrupt): added clic support on p4	2023-07-25 05:59:10 +00:00
Darian Leung	0c97fbd5ba	riscv: Remove redundant riscv_interrupts.h header ... This commit removes the riscv_interrupts.h header is it has become redundant. The previously exposed API has been handled as follows: - "riscv_interrupt_enable()" and "riscv_interrupt_disable()" have been removed. These functions were declarations only and never had any implementation. - "riscv_global_interrupts_enable()" and "riscv_global_interrupts_disable()" renamed to "rv_utils_intr_global_enable()" and "rv_utils_intr_global_disable()" respectively and now placed in rv_utils.h	2022-09-16 16:45:43 +08:00
Darian Leung	61eb7baa6b	esp_hw_support: Add esp_cpu.h abstraction and API ... This commit updates the esp_cpu.h API. The new API presents a new abstraction of the CPU where CPU presents the following interfaces: - CPU Control (to stall/unstall/reset the CPU) - CPU Registers (to read registers commonly used in SW such as SP, PC) - CPU Interrupts (to inquire/allocate/control the CPUs 32 interrupts) - Memory Port (to configure the CPU's memory bus for memory protection) - Debugging (to configure/control the CPU's debugging port) Note: Also added FORCE_INLINE_ATTR to the DoxyFile in order to pass doc builds for esp_cpu.h	2022-06-14 14:30:58 +08:00
Angus Gratton	fccab8f4ef	riscv: Add new arch-level component ... Changes come from internal branch commit a6723fc	2020-11-12 09:33:18 +11:00