Commit Graph

36 Commits

Author SHA1 Message Date
Laukik Hase
7c85d2c498
freertos: Indicate completed initialization for APP CPU with idle task hook
Co-authored-by: Mahavir Jain <mahavir@espressif.com>
2022-06-14 14:25:59 +05:30
Alexey Gerenkov
d06fac5c8b apptrace: Adds ESP32-C3 support 2022-05-13 16:23:46 +03:00
Alexey Gerenkov
fa6655cbcf apptrace: Refactors apptrace for better support various tracing HW 2022-05-13 08:45:31 +00:00
Alexey Gerenkov
dfd3a9c3bc riscv: Use semihosting to set breakpoint and watchpoint when running under debugger 2022-04-22 13:17:54 +03:00
Alexey Gerenkov
e688645ff9 riscv: Fixes GDB backtrace end function to point to prvTaskExitError 2022-04-22 12:38:16 +03:00
Marius Vikhammer
b30ff28034 freertos: always inline xPortSetInterruptMaskFromISR and vPortClearInterruptMaskFromISR
These were called from IRAM context where the caller expect them to be inlined
and accessible when cache is disabled. This was not the case when compiled with -O0.

Closes https://github.com/espressif/esp-idf/issues/8301
2022-03-03 10:09:33 +08:00
Angus Gratton
9f6e09d0d3 Merge branch 'bugfix/flash_rodata_any_alignement_v4.3' into 'release/v4.3'
build: Fix cache issue and add dedicated section for (Custom) App version info (backport v4.3)

See merge request espressif/esp-idf!13448
2021-06-22 00:23:49 +00:00
Marius Vikhammer
57442c38bd core: fix cases where riscv SP were not 16 byte aligned
RISC-V stack pointer should always be 16 byte aligned, but for some cases where
we were doing manual SP manipulation this was not always the case.
2021-06-02 16:02:10 +08:00
Ivan Grokhotkov
b7707c54ce freertos: fix TLS run-time address calculation
Since dd849ffc, _rodata_start label has been moved to a different
linker output section from where the TLS templates (.tdata, .tbss)
are located. Since link-time addresses of thread-local variables are
calculated relative to the section start address, this resulted in
incorrect calculation of THREADPTR/$tp registers.

Fix by introducing new linker label, _flash_rodata_start, which points
to the .flash.rodata output section where TLS variables are located,
and use it when calculating THREADPTR/$tp.

Also remove the hardcoded rodata section alignment for Xtensa targets.
Alignment of rodata can be affected by the user application, which is
the issue dd849ffc was fixing. To accommodate any possible alignment,
save it in a linker label (_flash_rodata_align) and then use when
calculating THREADPTR. Note that this is not required on RISC-V, since
this target doesn't use TPOFF.
2021-05-06 11:42:14 +08:00
Angus Gratton
7703fcbd8d Merge branch 'bugfix/silent_asserts_v4.3' into 'release/v4.3'
freertos/lw ip: Support silent assertions (v4.3)

See merge request espressif/esp-idf!13011
2021-04-13 04:30:09 +00:00
Angus Gratton
322cba0bf0 freertos: Add a small additional stack when optimization set to None
Fix for occasional crash on startup when DPORT task overwrites its stack during
context switch, otherwise.
2021-04-06 02:43:24 +00:00
Angus Gratton
f5c6595cb4 freertos: Increase minimum task stack size when stack smashing checker is enabled
Fixes issue with DPORT init task, this task uses minimum stack size and may not be
enough if stack smashing detection is set to Overall mode.

Also reworks the way we calculate minimum stack to allow for adding multiple
contributing factors.

Closes https://github.com/espressif/esp-idf/issues/6403
2021-04-06 02:43:24 +00:00
Angus Gratton
e9e2b68587 freertos: Use the standard assert() function for configASSERT
Unless the option for "assert and keep running" is enabled.

This means that silent asserts now work for FreeRTOS, and disabling asserts
now also disables them in FreeRTOS without needing a separate config change.

Related to https://github.com/espressif/esp-idf/issues/6306
2021-04-02 11:07:23 +11:00
Omar Chebib
774f010196 freertos: Fix delay between interrupt request and trigger on RISC-V
NOP instructions have been added in order to prevent the code
from executing code it shouldn't execute. This is due to a delay
between the moment an interrupt is requested and the moment it
is fired. It only happens on RISC-V SoC.
2021-03-10 12:14:21 +08:00
Angus Gratton
8e187e7157 Merge branch 'bugfix/c3_unit_test_cleanup_v4.3' into 'release/v4.3'
System: C3 shared stack watchpoint & unit test cleanups (v4.3)

See merge request espressif/esp-idf!12418
2021-02-24 22:51:11 +00:00
Marius Vikhammer
3d9523724d freertos: add API for getting tick rate on C3 2021-02-23 12:14:11 +08:00
Marius Vikhammer
360e7c4d51 system: enable shared stack watchpoint
Enable shared stack watchpoint for overflow detection

Enable unit tests:
 * "test printf using shared buffer stack" for C3
 * "Test vTaskDelayUntil" for S2
 * "UART can do poll()" for C3
2021-02-19 16:59:29 +08:00
Marius Vikhammer
04df1f3a42 CI: enable example builds for C3
Enables building C3 examples in CI.

Fixes related warnings/errors and disables examples that cannot run.
2021-02-09 12:04:02 +08:00
Angus Gratton
bc09dda0f4 docs: Update SMP descriptions for taskENTER_CRITICAL/taskEXIT_CRITICAL
Closes https://github.com/espressif/esp-idf/issues/6259
2021-02-05 10:18:23 +11:00
Ivan Grokhotkov
bb1f75179b Merge branch 'bugfix/freertos_systimer_stall_when_cpu_halted' into 'master'
freertos: stall systimer while CPU is in debug mode

See merge request espressif/esp-idf!12063
2021-01-29 07:02:30 +08:00
Angus Gratton
cc934ea0a1 Merge branch 'feature/esp32c3_tls' into 'master'
freertos: add thread local storage support in RISC-V port

Closes IDF-2125

See merge request espressif/esp-idf!12064
2021-01-27 15:19:06 +08:00
Marius Vikhammer
4374966d4e freerots: fix rtos_int_exit writing outside ISR stack
rtos_int_exit would store RA at an offset of 4 byte from the SP,
where the offset should be 0.

This caused rtos_int_exit to overwrite variables in bss.
2021-01-26 11:18:39 +00:00
Ivan Grokhotkov
b2aaebaf85 freertos: add thread local storage support in RISC-V port 2021-01-24 12:38:15 +00:00
Ivan Grokhotkov
d7bac619ec freertos: stall systimer while CPU is in debug mode 2021-01-24 11:32:17 +00:00
Li Shuai
63c4e5481f fix no RTOS SysTick interrupt for a period of time after the OS Scheduler is started 2021-01-19 14:51:22 +08:00
Li Shuai
355dd10257 light sleep: dfs support for esp32c3 2021-01-19 14:50:58 +08:00
Jakob Hasse
b51889dccb system: stack watchpoint support on C3
Closes IDF-2307
2021-01-14 17:46:44 +08:00
morris
753a929525 global: fix sign-compare warnings 2021-01-12 14:05:08 +08:00
morris
9e7d2c0065 esp32c3: format and clean up interrupt and os port code 2021-01-05 15:39:46 +08:00
Felipe Neves
544a3f7df5 interrupt-allocator: reject vector allocation if its marked as not-implemented. and search to next available 2021-01-05 15:39:46 +08:00
Felipe Neves
ec5acf91ee esp_shared_stack: enable shared stack function for riscv and reenable the unit test 2021-01-05 15:39:46 +08:00
Felipe Neves
f4781d3b1d freertos: riscv port now uses interrupt allocator and crosscore interrupt 2021-01-05 15:39:46 +08:00
Felipe Neves
810be86f21 freertos/riscv: move freertos aware interrupt code from vectors to the freertos riscv port.
The riscv vectors.S in riscv component contains the trap vector, which is responsible to
defer interrupts and examine if a task context switch is needed, this change cleans up
this code by hiding all freertos details behind on two functions rtos_it_enter/exit and
their implementations are placed in freertos riscv port files.
2021-01-05 15:39:46 +08:00
Ivan Grokhotkov
7f3b16a99d freertos: always enable static allocation
to use it for newlib locks
2020-12-29 16:18:04 +01:00
Angus Gratton
5228d9f9ce esp32c3: Apply one-liner/small changes for ESP32-C3 2020-12-01 10:58:50 +11:00
Angus Gratton
87e13baaf1 freertos: Add RISC-V port
Changes come from internal branch commit a6723fc
2020-11-13 07:49:11 +11:00