Configurable option to use IRAM as byte accessible memory (in single core mode) using
load-store (non-word aligned and non-word size IRAM access specific) exception handlers.
This allows to use IRAM for use-cases where certain performance penalty
(upto 170 cpu cycles per load or store operation) is acceptable. Additional configuration
option has been provided to redirect mbedTLS specific in-out content length buffers to
IRAM (in single core mode), allows to save 20KB per TLS connection.
DISABLED_FOR_TARGETS macros are used
Partly revert "ci: disable unavailable tests for esp32s2beta"
This partly reverts commit 76a3a5fb48a681c5d209931ea1b1038be201c0ec.
Partly revert "ci: disable UTs for esp32s2beta without runners"
This partly reverts commit eb158e9a22c5743cd116613bac74c92b560b957a.
Partly revert "fix unit test and examples for s2beta"
This partly reverts commit 9baa7826be9e2fcf194a934763f54d3ba0a677ba.
Partly revert "efuse: Add support for esp32s2beta"
This partly reverts commit db84ba868c4c7b266f1574a1dc500203630077d8.
heap_caps_malloc will fail to poison a block in IRAM with size not
divisible by 4. The proper fix will be to make poisoning code
smarter, or to disallow allocations from IRAM with size not aligned
by 4.
