11 Commits

Author	SHA1	Message	Date
Song Ruo Jing	6ad80f0332	refactor(uart): make uart driver as component, and fix astyle	2023-12-15 17:03:51 +08:00
morris	1c0be26531	fix(soc): soc header files can pass CI check	2023-06-26 23:00:45 +08:00
wuzhenghui	6fe405bffc	ci: fix failed ci test jobs	2023-06-21 15:24:50 +08:00
Marius Vikhammer	1a5e47bd07	ci: fixed test apps overriding pytest configs	2023-04-26 11:07:35 +08:00
laokaiyao	b7053b46ef	esp32h4: remove esp32h4 target from peripherals	2023-04-20 15:19:45 +08:00
Cao Sen Miao	fd3e0b0b18	esp32h2(ci): enable target test	2023-02-15 10:20:43 +08:00
jingli	2e4f0c7926	UT/esp32c2: reenable rtc clk calibration compensation UT	2023-02-02 20:26:08 +08:00
Song Ruo Jing	182e937c5a	clk_tree: Add basic clock support for esp32c6 ... - Support SOC ROOT clock source switch - Support CPU frequency change - Support RTC SLOW clock source switch - Support RTC SLOW clock + RC FAST calibration Remove FPGA build for esp32c6	2022-12-13 19:18:34 +08:00
Song Ruo Jing	7466ddfa8c	ci: Make consistence between pytest_*.py and .build-test-rules.yml for esp32c6 (i.e. to pass check_test_scripts_build_test_rules.py)	2022-11-28 11:58:30 +08:00
Song Ruo Jing	e13a4ad963	ci: Disable some unit-test-apps for esp32c6 to pass ci build stage	2022-11-28 11:58:30 +08:00
Marius Vikhammer	59e40fafba	esp_hw_support: move test to pytest	2022-11-25 16:21:35 +08:00