10 Commits

Author	SHA1	Message	Date
Martin Vychodil	7491ea677a	esp32s2: IRAM/DRAM memory protection ... * new mem_prot API * mem_prot on & locked by default (see Kconfig) * feature activated in start_cpu0_default() JIRA IDF-1355	2020-04-21 15:10:58 +02:00
Ivan Grokhotkov	f52952cb45	esp32: panic: do digital reset if cache error interrupt is set ... Even if frame->exccause != PANIC_RSN_CACHEERR, it is possible that the cache error interrupt status is set. For example, this may happen due to an invalid cache access in the panic handler itself. Check cache error interrupt status instead of frame->exccause to decide whether to do CPU reset or digital reset. Also remove unnecessary esp_dport_access_int_pause from esp_cache_err_get_cpuid, since the panic handler already calls esp_dport_access_int_abort on entry.	2019-12-30 09:49:07 +01:00
Anton Maklakov	afbaf74007	tools: Mass fixing of empty prototypes (for -Wstrict-prototypes)	2019-08-01 16:28:56 +07:00
Konstantin Kondrashov	399d2d2605	all: Using xxx_periph.h ... Using xxx_periph.h in whole IDF instead of xxx_reg.h, xxx_struct.h, xxx_channel.h ... . Cleaned up header files from unnecessary headers (releated to soc/... headers).	2019-06-03 14:15:08 +08:00
morris	f5b03c9ea3	misc adjustment of esp32 component	2019-04-03 19:57:46 +08:00
morris	956c25dedd	move esp32 chip specific includes to esp32/xxx.h	2019-03-18 17:14:05 +08:00
Ivan Grokhotkov	33cb16fd2a	esp32: fix cache error interrupt handler ... Cache error interrupt would read DPORT registers, which caused DPORT access protection to kick in. Disable DPORT protection before doing the reads.	2017-09-08 09:59:09 +08:00
Tian Hao	26a3cb93c7	component/soc : move dport access header files to soc ... 1. move dport access header files to soc 2. reduce dport register write protection. Only protect read operation	2017-05-09 18:06:00 +08:00
Tian Hao	f7e8856520	component/esp32 : fix dualcore bug ... 1. When dual core cpu run access DPORT register, must do protection. 2. If access DPORT register, must use DPORT_REG_READ/DPORT_REG_WRITE and DPORT_XXX register operation macro.	2017-05-08 21:53:43 +08:00
Jeroen Domburg	0b79d07d34	add detection of invalid cache access ... - fix level 4 interrupt vectors to produce correct backtrace - initialize invalid cache access interrupt on startup - handle invalid cache access in panic handler	2017-04-13 15:27:38 +08:00